vivado

There are 16 repositories under vivado topic.

LeiWang1999 / FPGA
帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目
fpga pynq verilog vivado xilinx
3341
hls4ml
fastmachinelearning / hls4ml
Machine learning on FPGAs using HLS
hls machine-learning fpga python keras pytorch onnx vivado vivado-hls neural-network intel-hls
Language:C++ 1105
hdl-util / hdmi
Send video/audio over HDMI on an FPGA
hdmi fpga dvi audio video systemverilog hdlmake quartus altera xilinx intel vivado
Language:SystemVerilog 1006
eugene-tarassov / vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
arty-a7 boom fpga genesys2 kc705 linux nexys-video risc-v riscv rocketchip vc707 vivado xilinx
Language:Tcl 736
prjxray
f4pga / prjxray
Documenting the Xilinx 7-series bit-stream format.
fpga xilinx xilinx-fpga artix artix7 kintex7 bitstream tools toolchain fuzzer vivado symbiflow
Language:Python 734
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 591
jofrfu / tinyTPU
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
fpga fpga-accelerator tensorflow tensor tpu vhdl zynq xilinx vivado assembly hardware-description-language hardware-designs hardware-acceleration hardware-architectures verilog ip-core embedded-systems linux internet-of-things iot
Language:VHDL 347
pavel-demin / red-pitaya-notes
Notes on the Red Pitaya Open Source Instrument
dsp fpga linux mca nmr radio red-pitaya redpitaya sdr tcl verilog vitis vivado vna wspr xilinx zynq
Language:Tcl 315
changwoolee / lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
vivado lenet high-level-synthesis hls sdsoc sdx accelerator cnn
Language:C++ 285
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 276
Xilinx / RapidWright
Build Customized FPGA Implementations for Vivado
xilinx rapidwright fpga vivado
Language:Java 270
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 252
ichi4096 / vivado-on-silicon-mac
Installs Vivado on M1/M2 macs
aarch64 arm arm64 docker fpga macos vivado vivado-installer
Language:C 195
Gowtham1729 / Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
verilog verilog-hdl verilog-project vhdl python3 basys3 basys-board basys fpga pixel convolution hsync basys3-fpga motion-blur ram python coe vivado image-processing digital-systems
Language:VHDL 157
hpcn-uam / Limago
Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
fpga hls network-stack vcu118 alveo-u200 vivado tcp 100gbe alveo-u280
Language:Tcl 112
Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition
车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
cv fpga-cortex-m3 vivado arm nexys4
Language:VHDL 111
UCLA-VAST / RapidStream
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
dataflow fpga hls parallel placement routing vivado
Language:Python 108
nxbyte / ARM-LEGv8
Verilog Implementation of an ARM LEGv8 CPU
verilog hennessy patterson arm-legv8-simulator arm isa pipeline-cpu hazard-detection forwarding-unit single-cycle multi-cycle ldr legv8-arm vivado xilinx
Language:Verilog 91
ilaydayaman / CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
cnn slr vivado fpga verilog
Language:Verilog 83
PyFPGA / pyfpga
A Python package to use FPGA development tools programmatically.
fpga python tcl xilinx intel microchip lattice ghdl ise libero quartus vivado yosys nextpnr icestorm trellis altera microsemi actel amd
Language:Python 76
tomas-fryza / vhdl-course
VHDL course at Brno University of Technology
brno-university-of-technology fpga vivado nexys-a7 vhdl teroshdl
Language:Tcl 74
WangXuan95 / Zynq-Tutorial
使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
zedboard zynq zynq-7020 vivado petalinux soc-fpga block-design
Language:C 74
hukenovs / intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
altera cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fpga integer-arithmetic radix-2 route-optimization verilog vhdl vivado xilinx
Language:VHDL 71
KeitetsuWorks / EBAZ4205
Vivado and PetaLinux projects for Zynq EBAZ4205 Board
fpga xilinx vivado petalinux zynq ebaz4205
Language:HTML 70
f4pga / prjuray
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
fpga xilinx xilinx-fpga ultrascale ultrascale-plus bitstream fuzzer vivado symbiflow
Language:SystemVerilog 66
HWAC-DL / hwac_object_tracker
FPGA accelerated TinyYOLO v2 object detection neural network
fpga pynq vivado tinyyolo detection verilog xilinx
Language:HTML 62
lauchinyuan / FPGA_QPSK-modem
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
fpga matlab qpsk verilog vivado
Language:Verilog 60
suoglu / Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
fpga vivado verilog hardware adder multiplier fixed-point floating-point binary16
Language:Verilog 53
li3tuo4 / rc-fpga-zcu
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
rocket-chip fpga-board vivado linux-boot risc-v zcu102 zynqmp
Language:Tcl 51
OVGN / OpenHBMC
Open-source high performance AXI4-based HyperRAM memory controller
fpga vivado xilinx
Language:Verilog 49
diogofferreira / fpga-miner
:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:
fpga bitcoin-miner xilinx-fpga vivado
Language:VHDL 45
tymonx / virtio
Virtio implementation in SystemVerilog
verilog systemverilog hdl rtl cmake verilator virtio quartus fpga xilinx vivado model systemc
Language:SystemVerilog 44
FDUCSLG / ICS-2021Spring-FDU
Introduction to Computer Systems (II), Spring 2021
nscscc mips vivado verilator systemverilog fpga
Language:C++ 42
MJoergen / HyperRAM
Portable HyperRAM controller
hyperram xilinx vivado artix fpga vhdl avalon intel altera lattice quartus modelsim questasim questa
Language:VHDL 42
sgherbst / svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
verilog systemverilog fixed-point floating-point synthesizable synthesis simulation vivado xcelium icarus-verilog iverilog xrun irun ncsim vcs icarus verilator
Language:SystemVerilog 41
25th-engineer / HFUT_2020_MIPS_CPU
合肥工业大学2020年《系统硬件综合设计》（《计算机组成原理》课程设计，CPU）的代码与报告；使用Verilog实现全冒险处理机制的MIPS五段流水CPU，支持MIPS-C3的50条指令。
cpu mips-c3 modelsim verilog vivado
Language:Assembly 39