There are 16 repositories under vivado topic.
Machine learning on FPGAs using HLS
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
Notes on the Red Pitaya Open Source Instrument
FPGA Accelerator for CNN using Vivado HLS
HDL support for VS Code
Installs Vivado on M1/M2 macs
Image Processing Toolbox in Verilog using Basys3 FPGA
车牌识别,FPGA,2019全国大学生集成电路创新创业大赛
[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
VHDL course at Brno University of Technology
使用 Vivado+PetaLinux 为 Xilinx Zynq7 搭建 Linux 系统 —— 以 Zedboard 为例
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Vivado and PetaLinux projects for Zynq EBAZ4205 Board
FPGA accelerated TinyYOLO v2 object detection neural network
16-bit Adder Multiplier hardware on Digilent Basys 3
Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:
合肥工业大学2020年《系统硬件综合设计》(《计算机组成原理》课程设计,CPU)的代码与报告;使用Verilog实现全冒险处理机制的MIPS五段流水CPU,支持MIPS-C3的50条指令。
Introduction to Computer Systems (II), Spring 2021