yosys

There are 4 repositories under yosys topic.

The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
130nm asic caravel foundry klayout magic netgen openram openroad rtl rtl2gds skywater soc-design system-on-chip verilog vlsi yosys
Language:Python 1316
cariboulabs / cariboulite
CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
defined fpga ice40 icestorm pi radio raspberry rf rpi sdr software yosys
Language:C 1083
m-labs / nmigen
A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen
fpga hdl nmigen yosys
Language:Python 651
nturley / netlistsvg
draws an SVG schematic from a JSON netlist
yosys klayjs diagram netlist visualization elk
Language:JavaScript 627
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 624
zachjs / sv2v
SystemVerilog to Verilog conversion
conversion systemverilog verilog yosys
Language:Haskell 540
efabless / caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
magic yosys caravel picorv32 vexriscv openroad openram sky130
Language:Verilog 283
apfelaudio / eurorack-pmod
A eurorack-friendly audio frontend compatible with many FPGA boards, based on the AK4619VN audio CODEC.
cocotb electronics eurorack fpga hardware kicad modular-synthesizers pmod synthesizer verilog yosys
Language:SystemVerilog 181
efabless / caravel_mpw-one
Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
caravel sky130 magic picorv32 openram openroad yosys
Language:Verilog 133
forflo / yodl
A VHDL frontend for Yosys
vhdl yosys
Language:C++ 102
fpga-tool-perf
chipsalliance / fpga-tool-perf
FPGA tool performance profiling
vpr fpga perf yosys arachne-pnr symbiflow conda-environment nextpnr toolchain performance-analysis f4pga
Language:Python 101
ECP5-PCIe / ECP5-PCIe
Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
pcie pcie-interface gateware fpga ecp5 yosys prjtrellis trellis nextpnr amaranth
Language:Python 92
scarv / xcrypto
XCrypto: a cryptographic ISE for RISC-V
risc-v riscv verilog formal-verification yosys icarus-verilog hardware hardware-acceleration cryptography instruction-set-architecture open-source mit-license crypto cpu ise research-project xcrypto
Language:Verilog 90
PyFPGA / pyfpga
A Python package to use FPGA development tools programmatically.
fpga python tcl xilinx intel microchip lattice ghdl ise libero quartus vivado yosys nextpnr icestorm trellis altera microsemi actel amd
Language:Python 86
lushaylabs / tangnano9k-series-examples
Examples for the Lushay Labs tang nano 9k series
apicula fpga nextpnr tangnano9k yosys
Language:GLSL 83
yosys-f4pga-plugins
chipsalliance / yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
yosys yosys-plugin eda fpga xilinx xilinx-fpga toolchain f4pga
Language:Verilog 82
dadamachines / doppler
Arduino compatible – Cortex M4F & FPGA Development Board
samd51 ice40up5k ice40 fpga arduino yosys icestorm
81
akilm / Physical-Design
Physical Design Flow from RTL to GDS using Opensource tools.
pad-cells chip physical-design opensource yosys picorv32 raven risc-v
75
mattvenn / fpga-sdft
sliding DFT for FPGA, targetting Lattice ICE40 1k
fpga verilog icestorm fft sdft yosys fourier
Language:Verilog 72
multigcs / LinuxCNC-RIO
RealtimeIO for LinuxCNC based on an FPGA
fpga linuxcnc linuxcnc-fpga ecp5 ice40 icestorm nextpnr yosys tangnano9k
Language:Python 71
YoWASP / yosys
Unofficial Yosys WebAssembly packages
fpga pypi python webassembly yosys yowasp
Language:Python 65
stnolting / neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
neorv32 fpga xilinx intel lattice ghdl yosys soc risc-v vhdl verilog
Language:VHDL 62
tmeissner / psl_with_ghdl
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
vhdl psl ghdl yosys formal-verification assertions symbiyosys functional-coverage
Language:VHDL 62
sphinxcontrib-hdl-diagrams
SymbiFlow / sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
sphinx sphinx-extension verilog fpga documentation-tool documentation yosys diagrams rtl hdl symbiflow
Language:Python 52
ben-marshall / croyde-riscv
A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
risc-v riscv64 microcontroller cpu verilog formal-verification micro-controller risc yosys cryptography crypto systemverilog verilator mit-license
Language:SystemVerilog 43
tmeissner / formal_hw_verification
Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl systemverilog yosys formal-verification verilog symbiyosys psl ghdl
Language:VHDL 41
ghdl / docker
Scripts to build and use docker images including GHDL
ghdl dockerfiles simulation testbench vhdl hardware ci gtkwave vunit actions yosys nextpnr icestorm synthesis pnr verilog prjtrellis openocd
Language:Shell 40
vmunoz82 / eda_tools
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
dockerfile eda yosys symbiyosys z3 boolector yices2 nextpnr-ice40 nextpnr-ecp5 nmigen verilator amaranth gowin openfpgaloader silice
Language:Dockerfile 39
embedded-explorer / Open-Source-RTL-Design
This repository documents the learning from VSD "RTL Design Using Verilog With SKY130 Technology" workshop
gate-level-simulation open-source-rtl vsd yosys
Language:Verilog 31
racerxdl / tangnano-yosys-hello
Sipeed Tang Nano Fully Opensource Toolchain Ledblink
fpga hello-world sipeed tang tang-nano yosys
Language:Makefile 30
mmicko / enigmaFPGA
Enigma in FPGA
fpga yosys ice40 blackice goboard verilog
Language:Verilog 26
risc8
osresearch / risc8
Mostly AVR compatible FPGA soft-core
fpga microcontroller up5k ice40 yosys softcore upduino
Language:Verilog 25
scarv / scarv-cpu
SCARV: a side-channel hardened RISC-V platform
riscv riscv32 xcrypto formal-verification yosys cryptography open-source mit-license crypto cpu ise instruction-set-architecture research-project verilator verilog
Language:Verilog 24
kivikakk / hdx
[mirror] HDL development environment on Nix.
amaranth-hdl hdl nix fpga nextpnr yosys
Language:Python 23
YosysHQ / padring
A padring generator for ASICs
asic chip eda vlsi yosys
Language:C++ 22
chili-chips-ba / openXC7-TetriSaraj
Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our special Video Controller in Basys3 Artix7-35T. Complemented with SW in the bare-metal 'C' they, together, make for this classic game. Except that it's now, in the standard BiH tradition, with a twist of our own.
basys3 fpga gamedev nextpnr open-source rtl tetris-game verilog-hdl xc7a35t xilinx yosys soc
Language:Verilog 18

yosys

The-OpenROAD-Project / OpenLane

cariboulabs / cariboulite

m-labs / nmigen

nturley / netlistsvg

olofk / edalize

zachjs / sv2v

efabless / caravel

apfelaudio / eurorack-pmod

efabless / caravel_mpw-one

forflo / yodl

chipsalliance / fpga-tool-perf

ECP5-PCIe / ECP5-PCIe

scarv / xcrypto

PyFPGA / pyfpga

lushaylabs / tangnano9k-series-examples

chipsalliance / yosys-f4pga-plugins

dadamachines / doppler

akilm / Physical-Design

mattvenn / fpga-sdft

multigcs / LinuxCNC-RIO

YoWASP / yosys

stnolting / neorv32-setups

tmeissner / psl_with_ghdl

SymbiFlow / sphinxcontrib-hdl-diagrams

ben-marshall / croyde-riscv

tmeissner / formal_hw_verification

ghdl / docker

vmunoz82 / eda_tools

embedded-explorer / Open-Source-RTL-Design

racerxdl / tangnano-yosys-hello

mmicko / enigmaFPGA

osresearch / risc8

scarv / scarv-cpu

kivikakk / hdx

YosysHQ / padring

chili-chips-ba / openXC7-TetriSaraj