rtl2gds

There are 2 repositories under rtl2gds topic.

The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1214
lakshmi-sathi / avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
pll clock-multiplier intellectual-property analog-circuit phase-detector charge-pump rtl2gds manufacturable ic asic
105
AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic openlane openlane-flow sky130 vlsi vlsi-physical-design rtl2gds
36
aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
asic openlane sky130 rtl2gds vlsi-physical-design linux openroad open-source hardware
14
hiiask / vsd_pll
8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
asic ic pll design analog-design google-skywater-pdk ngspice magic rtl2gds gds charge-pum clock-multiplier voltage-controlled-oscillator open-source open-source-hardware open-source-project
7
meeeeet / RTL-to-GDS-Implementation-of-SerDes
asic-design openroad rtl2gds verilog vlsi-physical-design
Language:Verilog 5

rtl2gds

The-OpenROAD-Project / OpenLane

lakshmi-sathi / avsdpll_1v8

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130

hiiask / vsd_pll

meeeeet / RTL-to-GDS-Implementation-of-SerDes