systemverilog

There are 76 repositories under systemverilog topic.

clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
haskell hardware-description-language fpga vhdl verilog systemverilog asic
Language:Haskell 1376
verible
chipsalliance / verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc
Language:C++ 1214
hdl-util / hdmi
Send video/audio over HDMI on an FPGA
hdmi fpga dvi audio video systemverilog hdlmake quartus altera xilinx intel vivado
Language:SystemVerilog 1023
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi axi4 axi4-lite systemverilog hardware network-on-chip asic fpga rtl ip
Language:SystemVerilog 936
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 594
trivialmips / nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
cpu fpga fpga-soc fpga-soc-linux mips systemverilog xilinx
Language:SystemVerilog 553
MikePopoloski / slang
SystemVerilog compiler and language services
verilog compiler systemverilog slang parse language-service
Language:C++ 540
TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
verilog vhdl systemverilog fpga
Language:JavaScript 506
splinedrive / kianRiscV
RISC-V Linux SoC, marchID: 0x2b
riscv verilog fpga cpu linux bare-metal linuxsoc mmu rv32ima sv32 systemverilog independent independentriscv
Language:AGS Script 492
zachjs / sv2v
SystemVerilog to Verilog conversion
conversion systemverilog verilog yosys
Language:Haskell 478
WangXuan95 / FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
fpga verilog systemverilog foc field-oriented-control motor bldc pmsm svpwm
Language:Verilog 440
dalance / svls
SystemVerilog language server
rust verilog systemverilog language-server
Language:Rust 418
veryl
veryl-lang / veryl
Veryl: A Modern Hardware Description Language
rtl rust systemverilog verilog
Language:Rust 407
openhwgroup / core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
risc-v systemverilog uvm verification
Language:Assembly 385
dalance / sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
rust rust-crate verilog systemverilog parser
Language:Rust 379
jamieiles / 80x86
80186 compatible SystemVerilog CPU core and FPGA reference design
fpga systemverilog x86 softcore 80186
Language:C++ 362
pymtl / pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
pymtl hardware-generation python hdl verilog systemverilog open-source-hardware multi-level-modeling cycle-level-modeling rtl open-source-eda
Language:Python 352
chipsalliance / Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
verilog parser python-api parser-ast vpi systemverilog preprocessor vpi-api vpi-standard antlr antlr4-grammar uvm linter elaboration
Language:C++ 331
WangXuan95 / USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
riscv risc-v rv32i soc fpga softcore rtl verilog systemverilog cpu
Language:SystemVerilog 320
taichi-ishitani / tvip-axi
AMBA AXI VIP
amba amba-axi axi axi4 systemverilog uvm vip
Language:SystemVerilog 300
dalance / svlint
SystemVerilog linter
rust verilog systemverilog lint linter
Language:Rust 284
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 280
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 277
Nic30 / hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
parser verilog fpga vhdl systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 python
Language:C++ 265
sv-tests
chipsalliance / sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
compliance-testing hdl rtl symbiflow systemverilog verilog
Language:SystemVerilog 259
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 254
veripool / verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
emacs-lisp systemverilog verilog verilog-mode
Language:SystemVerilog 240
WangXuan95 / FPGA-ftdi245fifo
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
usb ft232h ft600 ft601 fpga systemverilog ipcore verilog rtl
Language:Verilog 223
WangXuan95 / FPGA-SDcard-Reader
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
fpga rtl sdcard sd-card file-system verilog systemverilog sdio
Language:Verilog 217
Nic30 / hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
verilog vhdl fpga hls simulator hcl uvm systemverilog codegenerator codegen compiler rtl systemc
Language:Python 193
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 184
Juniper / open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
systemrdl jspec eda asic fpga registers uvm systemverilog register-descriptions systemrdl-compiler
Language:Verilog 182
chipsalliance / UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
ieee-standard listener serialization systemverilog vpi-api vpi-interface
Language:C++ 181
WangXuan95 / FPGA-CAN
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
can can-bus fpga verilog systemverilog rtl controller control-area-network
Language:Verilog 176
WangXuan95 / FPGA-JPEG-LS-encoder
An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。
fpga verilog systemverilog jpeg-ls jpegls jls rtl image-compression image-encoder
Language:Verilog 174
openhwgroup / core-v-mcu
This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
microcontroller systemverilog openhwgroup riscv
Language:SystemVerilog 158

systemverilog

clash-lang / clash-compiler

chipsalliance / verible

hdl-util / hdmi

pulp-platform / axi

olofk / edalize

trivialmips / nontrivial-mips

MikePopoloski / slang

TerosTechnology / vscode-terosHDL

splinedrive / kianRiscV

zachjs / sv2v

WangXuan95 / FPGA-FOC

dalance / svls

veryl-lang / veryl

openhwgroup / core-v-verif

dalance / sv-parser

jamieiles / 80x86

pymtl / pymtl3

chipsalliance / Surelog

WangXuan95 / USTC-RVSoC

taichi-ishitani / tvip-axi

dalance / svlint

rggen / rggen

mshr-h / vscode-verilog-hdl-support

Nic30 / hdlConvertor

chipsalliance / sv-tests

tymonx / logic

veripool / verilog-mode

WangXuan95 / FPGA-ftdi245fifo

WangXuan95 / FPGA-SDcard-Reader

Nic30 / hwt

suoto / hdl_checker

Juniper / open-register-design-tool

chipsalliance / UHDM

WangXuan95 / FPGA-CAN

WangXuan95 / FPGA-JPEG-LS-encoder

openhwgroup / core-v-mcu