systemverilog

There are 81 repositories under systemverilog topic.

clash-lang / clash-compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
asic fpga hardware-description-language haskell systemverilog verilog vhdl
Language:Haskell 1425
verible
chipsalliance / verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
analysis formatter hacktoberfest language-server-protocol lexer linter lsp-server parser productivity style-linter sv-lrm syntax-tree systemverilog systemverilog-developer systemverilog-parser verible yacc
Language:C++ 1332
hdl-util / hdmi
Send video/audio over HDMI on an FPGA
altera audio dvi fpga hdlmake hdmi intel quartus systemverilog video vivado xilinx
Language:SystemVerilog 1080
pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog
Language:SystemVerilog 1063
splinedrive / kianRiscV
RISC-V Linux SoC, marchID: 0x2b
riscv verilog fpga cpu linux bare-metal mmu rv32ima sv32 systemverilog independent independentriscv xv6
Language:C 691
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 624
MikePopoloski / slang
SystemVerilog compiler and language services
verilog compiler systemverilog slang parse language-service
Language:C++ 596
trivialmips / nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
cpu fpga fpga-soc fpga-soc-linux mips systemverilog xilinx
Language:SystemVerilog 570
TerosTechnology / vscode-terosHDL
VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
verilog vhdl systemverilog fpga
Language:VHDL 543
zachjs / sv2v
SystemVerilog to Verilog conversion
systemverilog verilog conversion yosys
Language:Haskell 540
WangXuan95 / FPGA-FOC
FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。
fpga verilog systemverilog foc field-oriented-control motor bldc pmsm svpwm
Language:Verilog 516
veryl
veryl-lang / veryl
Veryl: A Modern Hardware Description Language
rtl rust systemverilog verilog
Language:Rust 478
dalance / svls
SystemVerilog language server
rust verilog systemverilog language-server
Language:Rust 451
openhwgroup / core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
systemverilog uvm verification risc-v
Language:Assembly 429
dalance / sv-parser
SystemVerilog parser library fully compliant with IEEE 1800-2017
rust rust-crate verilog systemverilog parser
Language:Rust 396
jamieiles / 80x86
80186 compatible SystemVerilog CPU core and FPGA reference design
fpga systemverilog x86 softcore 80186
Language:C++ 372
pymtl / pymtl3
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
pymtl hardware-generation python hdl verilog systemverilog open-source-hardware multi-level-modeling cycle-level-modeling rtl open-source-eda
Language:Python 372
chipsalliance / Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
verilog parser python-api parser-ast vpi systemverilog preprocessor vpi-api vpi-standard antlr antlr4-grammar uvm linter elaboration
Language:C++ 357
taichi-ishitani / tvip-axi
AMBA AXI VIP
amba amba-axi axi axi4 systemverilog uvm vip
Language:SystemVerilog 354
WangXuan95 / USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
cpu fpga risc-v riscv rtl rv32i soc softcore systemverilog verilog
Language:SystemVerilog 347
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 319
dalance / svlint
SystemVerilog linter
rust verilog systemverilog lint linter
Language:Rust 304
mshr-h / vscode-verilog-hdl-support
HDL support for VS Code
verilog-hdl vscode systemverilog verilog language-server-client iverilog modelsim verilator ctags vivado bluespec-systemverilog systemverilog-support icarus-verilog svls hacktoberfest
Language:TypeScript 290
sv-tests
chipsalliance / sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
systemverilog symbiflow verilog hdl rtl compliance-testing
Language:SystemVerilog 285
Nic30 / hdlConvertor
Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
parser verilog fpga vhdl systemverilog systemverilog-parser vhdl-parser verilog-parser antrl4 python
Language:C++ 281
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 266
veripool / verilog-mode
Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
verilog emacs-lisp verilog-mode systemverilog
Language:SystemVerilog 256
WangXuan95 / FPGA-ftdi245fifo
FPGA-based USB fast data transmission using FT232H/FT600 chip. 使用FT232H/FT600芯片进行FPGA与电脑之间的高速数据传输。
usb ft232h ft600 ft601 fpga systemverilog ipcore verilog rtl
Language:Verilog 256
WangXuan95 / FPGA-SDcard-Reader
An FPGA-based SD-card reader to read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器，可以从FAT16或FAT32格式的SD卡中读取文件。
fpga rtl sdcard sd-card file-system verilog systemverilog sdio
Language:Verilog 254
WangXuan95 / FPGA-CAN
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
can can-bus fpga verilog systemverilog rtl controller control-area-network
Language:Verilog 208
Nic30 / hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
verilog vhdl fpga hls simulator hcl uvm systemverilog codegenerator codegen compiler rtl systemc
Language:Python 200
WangXuan95 / FPGA-JPEG-LS-encoder
An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码器，可实现高压缩率的无损/近无损图像压缩。
fpga verilog systemverilog jpeg-ls jpegls jls rtl image-compression image-encoder
Language:Verilog 199
chipsalliance / UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
vpi-api vpi-interface systemverilog listener serialization ieee-standard
Language:C++ 193
Juniper / open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
asic eda fpga jspec register-descriptions registers systemrdl systemrdl-compiler systemverilog uvm
Language:Verilog 192
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 192
pulp-platform / cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
fpga riscv rtl-design simulation systemverilog asic
Language:Verilog 185

systemverilog

clash-lang / clash-compiler

chipsalliance / verible

hdl-util / hdmi

pulp-platform / axi

splinedrive / kianRiscV

olofk / edalize

MikePopoloski / slang

trivialmips / nontrivial-mips

TerosTechnology / vscode-terosHDL

zachjs / sv2v

WangXuan95 / FPGA-FOC

veryl-lang / veryl

dalance / svls

openhwgroup / core-v-verif

dalance / sv-parser

jamieiles / 80x86

pymtl / pymtl3

chipsalliance / Surelog

taichi-ishitani / tvip-axi

WangXuan95 / USTC-RVSoC

rggen / rggen

dalance / svlint

mshr-h / vscode-verilog-hdl-support

chipsalliance / sv-tests

Nic30 / hdlConvertor

tymonx / logic

veripool / verilog-mode

WangXuan95 / FPGA-ftdi245fifo

WangXuan95 / FPGA-SDcard-Reader

WangXuan95 / FPGA-CAN

Nic30 / hwt

WangXuan95 / FPGA-JPEG-LS-encoder

chipsalliance / UHDM

Juniper / open-register-design-tool

suoto / hdl_checker

pulp-platform / cheshire