openroad
There are 7 repositories under openroad topic.
- skywater-pdk
google / skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
Language:Python 3078 The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Language:Verilog 1814OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language:Python 1440- gf180mcu-pdk
PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).
Language:Makefile 385 OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language:Verilog 385efabless / caravel
Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
Language:Verilog 319The next generation of OpenLane, rewritten from scratch with a modular architecture
Language:Python 275Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Language:Verilog 134- open-source-pdks
Index of the fully open source process design kits (PDKs) maintained by Google.
- globalfoundries-pdk-libs-gf180mcu_fd_pr
Primitives for GF180MCU provided by GlobalFoundries.
Language:Python 48 daquintero / piel
Photonic Integrated ELectronics. Microservices to codesign photonics, electronics, quantum, and more.
Language:Python 44- skywater-pdk-libs-sky130_fd_pr_reram
SKY130 ReRAM and examples (SkyWater Provided)
- globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0
7 track standard cells for GF180MCU provided by GlobalFoundries.
Language:Verilog 26 - globalfoundries-pdk-ip-gf180mcu_fd_ip_sram
SRAM macros created for the GF180MCU provided by GlobalFoundries.
Language:Verilog 17 - globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu9t5v0
9 track standard cells for GF180MCU provided by GlobalFoundries.
Language:Verilog 16 - skywater-pdk-libs-sky130_fd_sc_hd
"High density" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 16 aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
- Language:Verilog 15
- globalfoundries-pdk-libs-gf180mcu_fd_io
IO and periphery cells for the GF180MCU provided by GlobalFoundries.
Language:Verilog 13 The source code that empowers OpenROAD Cloud
- Language:Python 12
- globalfoundries-pdk-libs-gf180mcu_fd_bd_sram
SRAM build space for the GF180MCU provided by GlobalFoundries.
- globalfoundries-pdk-libs-gf180mcu_osu_sc
Digital standard cells for GF180MCU provided by Oklahoma State University.
nishit0072e / RTL-to-GDSII
Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout generation
Language:C++ 7- skywater-pdk-libs-sky130_fd_sc_hdll
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 6 - skywater-pdk-libs-sky130_fd_sc_lp
"Low power" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 6 - skywater-pdk-libs-sky130_fd_sc_hs
"High speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 5 - skywater-pdk-libs-sky130_fd_sc_ls
"Low speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 5 - skywater-pdk-libs-sky130_fd_sc_ms
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 5 - skywater-pdk-libs-sky90fd_fd_sc
Standard cells for SKY90FD provided by SkyWater.
- Language:Python 5
- skywater-pdk-libs-sky130_fd_sc_hvl
"High voltage" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 4 - skywater-pdk-libs-sky90fd_osu_sc
Standard cells for SKY90FD provided by Oklahoma State University.
Bynaryman / SUF
SUF is a SUperset Framework for OpenROAD that acts as an enhancement graft by augmenting the original capabilities.
Language:Python 3- openroad-dockerLanguage:Dockerfile 3
rahulearn2019 / msvsdpim
Physical Design of Mixed signal circuit that performs- "In Memory logic using 8TSRAM cells" using OPENFASOC.
Language:Python 2
