vlsi-physical-design

There are 18 repositories under vlsi-physical-design topic.

limbo018 / DREAMPlace
Deep learning toolkit-enabled VLSI placement
vlsi-physical-design deep-learning pytorch vlsi vlsi-placement gpu-acceleration
Language:C++ 615
OpenTimer / OpenTimer
A High-performance Timing Analysis Tool for VLSI Systems
static-timing-analysis sta vlsi vlsi-circuits vlsi-physical-design cpp17 parallel-computing circuit-simulator verilog electronic-design-automation computer-aided-design eda cad circuit-simulation circuit-analysis
Language:Verilog 511
cuhk-eda / dr-cu
Dr. CU, VLSI Detailed Routing Tool Developed by CUHK
eda vlsi-physical-design routing
Language:C++ 119
AUCOHL / DFFRAM
Standard Cell Library based Memory Compiler using FF/Latch cells
verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design
Language:Verilog 118
OpenTimer / Parser-Verilog
A Standalone Structural Verilog Parser
cpp17 flex bison-yacc computer-aided-design electronic-design-automation eda verilog vlsi-physical-design vlsi-circuits circuit
Language:Verilog 73
luckyrantanplan / nthu-route
VLSI EDA Global Router
vlsi vlsi-physical-design vlsi-circuits router eda globalrouter electronic-design-automation ispd lattice-graph multi-maze-routing
Language:C++ 57
OpenTimer / Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
static-timing-analysis cpp17 computer-aided-design electronic-design-automation eda sta parasitic spef vlsi vlsi-physical-design vlsi-circuits circuits
Language:C++ 47
ieee-ceda-datc / RDF-2019
DATC RDF
vlsi vlsi-physical-design eda vlsi-cad ieee-ceda ieee-ceda-datc design-flow vlsi-design-flow cad design-automation placement routing clock-tree logic-synthesis
Language:Verilog 46
chengengjie / salt
Steiner Shallow-Light Tree for VLSI Routing
graph-algorithms routing vlsi-physical-design eda
Language:C++ 40
VLSI-Physical-Design-Automation
twweeb / VLSI-Physical-Design-Automation
Courseworks of CS6165 VLSI Physical Design Automation, NTHU.
physical-design-automation vlsi-physical-design vlsi vlsi-cad vlsi-placement vlsi-floorplan vlsi-design vlsi-routing two-way-min-cut fixed-outline global-placement global-routing nthu eda
Language:C++ 39
coriolis
lip6 / coriolis
Coriolis VLSI EDA Tool (LIP6)
eda vlsi-physical-design
Language:C++ 38
AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
asic openlane openlane-flow sky130 vlsi vlsi-physical-design rtl2gds
36
shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified
vlsi-physical-design risc-v electronics-engineering
Language:Verilog 32
ShonTaware / OpenSource_Physical_Design
This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
open-source openlane-flow vlsi-physical-design sky130
28
andrsmllr / magic_vlsi_examples
Some simple examples for the Magic VLSI physical chip layout tool.
vlsi vlsi-physical-design asic
27
jinwookjungs / lefdef_util
A LEF/DEF Utility.
vlsi vlsi-physical-design lef def-parser def placement vlsi-placement bookshelf lef-parser datc-rdf
Language:Prolog 25
hibagus / 64pointFFTProcessor
Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.
digital-signal-processing signal-processing fast-fourier-transform vlsi-design vlsi-physical-design vlsi-project fpga-accelerator
Language:Verilog 24
fayizferosh / yosys-tcl-ui-report
5 Day TCL begginer to advanced training workshop by VSD
bash linux open-source opentimer shell-scripting static-timing-analysis synthesis tcl tcl-extensions tcl-procedures tcl-programming vlsi-physical-design workshop yosys eda-tools csv hardware-description-language
Language:Verilog 15
aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
asic openlane sky130 rtl2gds vlsi-physical-design linux openroad open-source hardware
14
jnestor / CADApps
VLSI CAD Algorithm Visualizations implemented as Java Applications
vlsi-physical-design visualizations java-applications lafayette-cadapps cadapplets
Language:Java 12
curry0622 / VLSI-Physical-Design-Automation
NTHU CS6135 VLSI Physical Design Automation (2022 Fall)
eda vlsi vlsi-physical-design vlsi-pda nthucs
Language:Prolog 10
ganeshgore / spydrnet-physical
This is a SpyDrNet Plugin for a physical design related transformations
automation vlsi-physical-design netlist hdl verilog spydrnet
Language:Python 10
UdayaShankarS / TCL-Scripting
Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference
tcl-scripts vlsi-cad vlsi-physical-design
Language:Tcl 10
en9inerd / SimAn
Standard cell placement (global and detailed) tool based on modified algorithm “simulated annealing”
vlsi-physical-design algorithm
Language:C++ 9
Koyama-Tsubasa / VLSI_Physical_Design_Automation
Coursework of NTHU CS613500 VLSI Physical Design Automation
eda physical-design-automation two-way-min-cut vlsi vlsi-floorplan vlsi-physical-design nthu fixed-outline vlsi-placement vlsi-routing cad iccad partitioning-algorithms
Language:C++ 7
virginrobotics / 5-Stage-2.92-Ghz-CMOS-VCO
This is a documentation of the steps involved in designing a VCO on the SYNOPSYS Custom Compiler - 28nm PDK
analog vlsi-physical-design
7
harshithsn / Universal-Shift-Register
This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-source EDA tool which gives RTL to GDSII flow.
openlane openlane-flow universal-shift-register vlsi-physical-design vlsi
Language:Verilog 6
ieee-ceda-datc / datc-rdf
IEEE DATC Robust Design Flow 2021.
vlsi vlsi-physical-design eda design-automation
Language:Verilog 6
lip6 / alliance
Alliance VLSI CAD Tools (LIP6)
eda vlsi-physical-design
Language:C 6
Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
bluespec bluespec-systemverilog bluespec-systemverilog-language processor-design processor-architecture vector-processor ram bus hardware hardware-designs hardware-acceleration processor vlsi-cad vlsi vlsi-physical-design vlsi-design
Language:Bluespec 6
srgrr / CellRouter
A SAT-Based cell router.
academic sat cell-routing python3 combinatorial-optimization vlsi-physical-design graph-algorithms
Language:C++ 6
vlsi-cmos-inverter-design-magic
trojanink / vlsi-cmos-inverter-design-magic
VLSI Design, Magic, OpenCircuitDesign,CMOS VLSI Design, CMOS Inverter Magic
vlsi-physical-design vlsi-circuits vlsi cmos pmos magic inverter circuit
6
andrsmllr / magic_vlsi_sky130_examples
Some simple examples for the Magic VLSI physical chip layout tool using Google Skywater130 PDK.
vlsi examples asic layout vlsi-physical-design asic-design
5
enzoleo / RePlAce
A customized placer based on the RePlAce global placement tool.
vlsi vlsi-physical-design vlsi-placement global-placement
Language:C++ 5
karthik-r-rao / VLSI_Physical_Design_Tool
A simple tool to demonstrate the physical design steps of VLSI Design Flow.
vlsi vlsi-physical-design vlsi-cad vlsi-project vlsi-design
Language:Python 5
A-Primer-For-Physical-Design-Automation
neeraj1397 / A-Primer-For-Physical-Design-Automation
This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.
algorithms asic-design python3 vlsi-cad vlsi-physical-design eda vlsi-design vlsi-pda
Language:Jupyter Notebook 5

vlsi-physical-design

limbo018 / DREAMPlace

OpenTimer / OpenTimer

cuhk-eda / dr-cu

AUCOHL / DFFRAM

OpenTimer / Parser-Verilog

luckyrantanplan / nthu-route

OpenTimer / Parser-SPEF

ieee-ceda-datc / RDF-2019

chengengjie / salt

twweeb / VLSI-Physical-Design-Automation

lip6 / coriolis

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK

ShonTaware / OpenSource_Physical_Design

andrsmllr / magic_vlsi_examples

jinwookjungs / lefdef_util

hibagus / 64pointFFTProcessor

fayizferosh / yosys-tcl-ui-report

aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130

jnestor / CADApps

curry0622 / VLSI-Physical-Design-Automation

ganeshgore / spydrnet-physical

UdayaShankarS / TCL-Scripting

en9inerd / SimAn

Koyama-Tsubasa / VLSI_Physical_Design_Automation

virginrobotics / 5-Stage-2.92-Ghz-CMOS-VCO

harshithsn / Universal-Shift-Register

ieee-ceda-datc / datc-rdf

lip6 / alliance

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

srgrr / CellRouter

trojanink / vlsi-cmos-inverter-design-magic

andrsmllr / magic_vlsi_sky130_examples

enzoleo / RePlAce

karthik-r-rao / VLSI_Physical_Design_Tool

neeraj1397 / A-Primer-For-Physical-Design-Automation