verilog-simulator

There are 4 repositories under verilog-simulator topic.

verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
verilog system-verilog verilog-simulator verilator compilers cpp systemc rtl
Language:C++ 3157
f4pga-arch-defs
f4pga / f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
fpga ice40 sphinx documentation verilog hdl xilinx-fpga artix kintex7 architecture-definitions verilog-simulator vpr primitives lattice toolchain synthesis python artix7 verilog-simulations symbiflow
Language:Jupyter Notebook 295
neelkshah / MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog
computer-architecture computer-organization computer-organisation microprocessor microprocessors bits-pilani verilog verilog-hdl verilog-project verilog-programs verilog-components verilog-snippets verilog-simulator mips-processor mips-architecture mips-instructions
Language:Verilog 135
Arjun-Narula / Traffic-Light-Controller-using-Verilog
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
verilog verilog-hdl verilog-project verilog-code verilog-programs verilog-simulator vivado vivado-hls vivado-simulator traffic traffic-light traffic-sign-recognition
Language:JavaScript 48
JeffDeCola / my-verilog-examples
A place to keep my synthesizable verilog examples.
systemverilog gtkwave iverilog hardware-description-language verilog hardware asic-design fpga vivado asic hdl synthesize verilog-simulator simulator waveform xilinx hardware-architecture synthesis
Language:Verilog 47
mateuspinto / FPGA_Verilog_Ballot_Box-TP2-ISL-UFV
Hardware description of a complete Ballot Box made in Verilog with implementation in FPGA-Altera-DE-2-155, made in Verilog with Quartus Prime in discipline ISL for computer science graduation.
verilog verilog-hdl verilog-project verilog-simulator fpga fpga-firmware altera-fpga altera-de2
Language:Verilog 6
vb000 / vcs-slave-mode
Example to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
synopsys-vcs verilog-simulator shared-object
Language:Makefile 5
cw1997 / verilog-parser
Verilog HDL Parser
parser parsers verilog verilog-hdl verilog-simulator
Language:ANTLR 4
AUCOHL / Classic-Playground
A playground based on the classic version of the Cloud V IDE
eda verilog verilog-hdl verilog-simulator online-ide
Language:JavaScript 3
ali-asnaashari / Computer_Architecture_Lab
Computer Architecture Lab Course 2022/1400, Fall CSE & IT Dept., Shiraz University
verilog architecture architecture-lab mips-architecture verilog-simulator
Language:Verilog 1
galihru / logicsim
The Logic Simulator is an advanced tool designed to facilitate the understanding of sequential circuit design. This application implements fundamental concepts of computer architecture and digital systems engineering through an intuitive drag-and-drop interface, providin
logic-gates logic-simulator pwa-apps verilog-hdl verilog-project verilog-simulator
Language:JavaScript 1
jElhamm / Verilog-HDL-Codes-Collection
"Repository containing a collection of Verilog code modules and test bench for digital design projects. "
7segment alu comparator counter decoder encoder gates multiplexer shiftregister testbench testbench-generator-verilog verilog verilog-hdl verilog-programs verilog-project verilog-simulator
Language:Verilog 1
ShiV-0312 / MIPS_PROCESSOR
32-bits MIPS Processor with 5-stage pipeline
verilog verilog-project verilog-code mips mips-processor mips32 verilog-simulator
Language:Verilog 1
wasifijaz / Digital-System-Design-Verilog-Implementation
Digital System Design Verilog Implementation
digital-system-design verilog verilog-code verilog-simulator lifo fifo logic-gates adders subtractor
Language:Verilog 1
Bhargav-962 / 4-bit_Register-Verilog
A verilog program that mimics the circuitry of a 4-bit register implemented with four 4x1 multiplexers and four D-Flipflops
verilog-simulator
Language:Verilog 0
Rudra-Joshi-002 / Verilog_Codes
This Repository shows the implementation and results of various codes that I write in Verilog HDL
verilog verilog-code verilog-hdl verilog-programs verilog-project verilog-simulator
Language:Verilog 0
gokcedemir / Mips-processor
32-bit MIPS processor fully supporting all core instructions
32-bits mips-processor verilog-simulator
Language:Verilog
thuvasooriya / verilator
build verilator with zig
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator zig zig-package
Language:Zig