axi4-lite

There are 0 repository under axi4-lite topic.

pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
axi axi4 axi4-lite systemverilog hardware network-on-chip asic fpga rtl ip
Language:SystemVerilog 945
OSVVM / AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
osvvm axi4 axi4-lite axi4-stream verification vhdl vip verification-component tlm testbench simulation simulation-modeling
Language:VHDL 103
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
axi4 axi4-lite axi4-protocol axi4-full crossbar interconnect fpga fpga-soc processor asic-design asic soc amba arm verilog riscv riscv32 riscv64 monodraw
Language:SystemVerilog 90
ultraembedded / core_usb_host
Basic USB 1.1 Host Controller for small FPGAs
usb-host axi4-lite utmi fpga ulpi usb
Language:C 81
ultraembedded / core_audio
Audio controller (I2S, SPDIF, DAC)
i2s spdif dac audio axi4-lite verilog fpga
Language:Verilog 74
mmxsrup / axi4-interface
AXI4 and AXI4-Lite interface definitions
axi4 axi4-lite fpga systemverilog axi4-stream
Language:SystemVerilog 67
ultraembedded / core_usb_bridge
USB -> AXI Debug Bridge
usb fpga verilog usb-cdc axi4-lite
Language:Verilog 32
ic-lab-duth / NoCpad
HLS for Networks-on-Chip
cache-coherence axi4 axi4-lite network-on-chip high-level-synthesis noc hls
Language:C++ 26
somyadashora / AMBA-AXI4-Lite
Master and Slave made using AMBA AXI4 Lite protocol.
amba axi4-lite design verilog
Language:Stata 20
dpretet / meduram
Multi-port BRAM IP for ASIC and FPGA
bram ram amba axi4 fpga svut yosys iverilog block fusesoc asic axi4-lite axi4-lite-interface multi-port
Language:SystemVerilog 10
MicroTCA-Tech-Lab / hectare
VHDL generator from SystemRDL
vhdl fpga axi4-lite systemrdl
Language:Python 6
krailis / zynq-axi-tutorial
A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
amba-axi axi4-lite axi4-stream-interfaces high-level-synthesis petalinux tcl vivado
Language:Tcl 4
rlee287 / hardware-bus-infrastructure
A collection of formal properties for hardware buses, and cores using them.
bus-standards axi4 psl sva axi4-stream wishbone-bus axi4-lite
Language:Verilog 4
zdzislaw-s / oled-driver-demo
OLED driver demo running on ZedBoard
zedboard oled-display oled-display-ssd1306 ssd1306 freertos c-plus-plus verilog vivado xilinx-fpga xilinx-vivado animation axi4-lite spi zynq hardware bitstream sdk
Language:PHP 3
CSpyridakis / Reconfigurable-Computing
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
vhdl hls fpga rsoc zynq zynq-7000 reconfigurable-computing evaluation-board xilinx vivado axi4-protocol axi4-stream-protocol vivado-hls axi4-lite axi4
Language:C++ 2
dougsummerville / Simple-AXI-SPI-Peripheral
A Custom AXI4 SPI Peripheral
spi hdl axi4-lite xilinx-vivado
Language:VHDL 1
Gabriele-bot / Base2_Log
Hardware implementation of a base 2 logarithm
logarithm verilog lookup-table python3 fpga axi4-lite
Language:Jupyter Notebook 0
supleed2 / axiTest
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
axi4-lite systemverilog verilator work-in-progress
Language:SystemVerilog 0

axi4-lite

pulp-platform / axi

OSVVM / AXI4

dpretet / axi-crossbar

ultraembedded / core_usb_host

ultraembedded / core_audio

mmxsrup / axi4-interface

ultraembedded / core_usb_bridge

ic-lab-duth / NoCpad

somyadashora / AMBA-AXI4-Lite

dpretet / meduram

MicroTCA-Tech-Lab / hectare

krailis / zynq-axi-tutorial

rlee287 / hardware-bus-infrastructure

zdzislaw-s / oled-driver-demo

CSpyridakis / Reconfigurable-Computing

dougsummerville / Simple-AXI-SPI-Peripheral

Gabriele-bot / Base2_Log

supleed2 / axiTest