axi4-lite

There are 0 repository under axi4-lite topic.

pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog
Language:SystemVerilog 1397
dpretet / axi-crossbar
An AXI4 crossbar implementation in SystemVerilog
amba arm asic asic-design axi4 axi4-full axi4-lite axi4-protocol crossbar fpga fpga-soc interconnect monodraw processor riscv riscv32 riscv64 soc verilog
Language:SystemVerilog 178
OSVVM / AXI4
AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
axi4 axi4-lite axi4-stream osvvm simulation simulation-modeling testbench tlm verification verification-component vhdl vip
Language:VHDL 143
mmxsrup / axi4-interface
AXI4 and AXI4-Lite interface definitions
axi4 axi4-lite fpga systemverilog axi4-stream
Language:SystemVerilog 96
ultraembedded / core_usb_host
Basic USB 1.1 Host Controller for small FPGAs
usb-host axi4-lite utmi fpga ulpi usb
Language:C 95
ultraembedded / core_audio
Audio controller (I2S, SPDIF, DAC)
i2s spdif dac audio axi4-lite verilog fpga
Language:Verilog 90
ultraembedded / core_usb_bridge
USB -> AXI Debug Bridge
usb fpga verilog usb-cdc axi4-lite
Language:Verilog 40
ic-lab-duth / NoCpad
HLS for Networks-on-Chip
axi4 axi4-lite cache-coherence high-level-synthesis hls network-on-chip noc
Language:C++ 36
somyadashora / AMBA-AXI4-Lite
Master and Slave made using AMBA AXI4 Lite protocol.
amba axi4-lite verilog design
Language:Stata 28
VHDL / Interfaces
Interface definitions for VHDL-2019.
axi4 axi4-lite axi4-stream ethernet i2c i2s interface mipi modeview record uart vhdl
Language:VHDL 27
arhamhashmi01 / Axi4-lite
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
axi4-lite axi4-lite-interface systemverilog axi4-protocol verilator vivado-simulator hardware-designs
Language:SystemVerilog 12
dpretet / meduram
Multi-port BRAM IP for ASIC and FPGA
amba asic axi4 axi4-lite axi4-lite-interface block bram fpga fusesoc iverilog multi-port ram svut yosys
Language:SystemVerilog 12
MicroTCA-Tech-Lab / hectare
VHDL generator from SystemRDL
vhdl fpga axi4-lite systemrdl
Language:Python 9
krailis / zynq-axi-tutorial
A tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
amba-axi axi4-lite axi4-stream-interfaces high-level-synthesis tcl vivado petalinux
Language:Tcl 4
rlee287 / hardware-bus-infrastructure
A collection of formal properties for hardware buses, and cores using them.
bus-standards axi4 psl sva axi4-stream wishbone-bus axi4-lite
Language:Verilog 4
zdzislaw-s / oled-driver-demo
OLED driver demo running on ZedBoard
animation axi4-lite bitstream c-plus-plus freertos hardware oled-display oled-display-ssd1306 sdk spi ssd1306 verilog vivado xilinx-fpga xilinx-vivado zedboard zynq
Language:PHP 3
CSpyridakis / Reconfigurable-Computing
Introduction in Reconfigurable Computing (using reconfigurable Systems-on-Chip rSoC)
vhdl hls fpga rsoc zynq zynq-7000 reconfigurable-computing evaluation-board xilinx vivado axi4-protocol axi4-stream-protocol vivado-hls axi4-lite axi4
Language:C++ 2
dougsummerville / Simple-AXI-SPI-Peripheral
A Custom AXI4 SPI Peripheral
spi hdl axi4-lite xilinx-vivado
Language:VHDL 2
muhammadtalhasami / Axi4_lite_interface
This repo contains an implementation of Axi4 lite interface on system verilog. Verilator and Vivado tools are used .
axi4 axi4-lite axi4-lite-interface axi4-lite-system-verilog axi4-protocol system-verilog verilator vivado
Language:SystemVerilog 2
JN513 / verilog-buses-implementations
Popular bus implementations in Verilog HDL
ahb apb avalon axi4 axi4-lite axi4-stream fpga i2c i2c-bus spi verilog verilog-hdl
Language:Verilog 1
supleed2 / axiTest
AXI4-Lite compatible Driver module for use with Verilator and other DPI-C compatible simulators.
axi4-lite systemverilog verilator work-in-progress
Language:SystemVerilog 1
Gabriele-bot / Base2_Log
Hardware implementation of a base 2 logarithm
axi4-lite fpga logarithm lookup-table python3 verilog
Language:Jupyter Notebook 0
dighrasker / MultiCore_L2_Cache
A UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.
axi4-lite mesi-protocol rtl-design uvm-verification
Language:SystemVerilog
muhammadtalhasami / peripherals
This repo is based on the implementation of different peripherals and protocols like Axi4-lite , i2c and spi.
axi4-lite i2c peripherals spi
Language:SystemVerilog
qubeck78 / axiTemplates
AXI4 templates. Provide easy starting point for developing: AXI4-Lite slave, AXI4-full master
axi4 axi4-full axi4-lite vhdl zynq-7000

axi4-lite

pulp-platform / axi

dpretet / axi-crossbar

OSVVM / AXI4

mmxsrup / axi4-interface

ultraembedded / core_usb_host

ultraembedded / core_audio

ultraembedded / core_usb_bridge

ic-lab-duth / NoCpad

somyadashora / AMBA-AXI4-Lite

VHDL / Interfaces

arhamhashmi01 / Axi4-lite

dpretet / meduram

MicroTCA-Tech-Lab / hectare

krailis / zynq-axi-tutorial

rlee287 / hardware-bus-infrastructure

zdzislaw-s / oled-driver-demo

CSpyridakis / Reconfigurable-Computing

dougsummerville / Simple-AXI-SPI-Peripheral

muhammadtalhasami / Axi4_lite_interface

JN513 / verilog-buses-implementations

supleed2 / axiTest

Gabriele-bot / Base2_Log

dighrasker / MultiCore_L2_Cache

muhammadtalhasami / peripherals

qubeck78 / axiTemplates