wishbone-bus

There are 1 repository under wishbone-bus topic.

ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
fpga soft-core cross-compiler verilog verilator wishbone wishbone-bus zipcpu cpu risc-cpu
Language:Verilog 1197
ZipCPU / wb2axip
Bus bridges and other odds and ends
fpga wishbone wishbone-bus axi-bus xilinx xilinx-vivado gplv3
Language:Verilog 438
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 280
ZipCPU / wbuart32
A simple, basic, formally verified UART controller
fpga uart uart-verilog verilator wishbone wishbone-bus verilog serialport
Language:Verilog 254
ZipCPU / autofpga
A utility for Composing FPGA designs from Peripherals
wishbone-bus wishbone fpga c-plus-plus verilog verilator
Language:C++ 157
ZipCPU / sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
sd-card sd-interface fpga verilog-components verilog verilator wishbone wishbone-bus spi-interface axi emmc sdio
Language:Verilog 139
ZipCPU / openarty
An Open Source configuration of the Arty platform
zipcpu fpga fpga-soc arty verilator wishbone-bus wishbone
Language:Verilog 116
jakubcabal / uart-for-fpga
Simple UART controller for FPGA written in VHDL
uart fpga uart-controller vhdl controller wishbone wishbone-bus uart-loopback simulation ghdl cyc1000
Language:VHDL 89
ZipCPU / wbscope
A wishbone controlled scope for FPGA's
fpga verilog verilator debugging-tools wishbone-bus wishbone
Language:Verilog 70
lxp32-cpu
lxp32 / lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga cpu risc soft-core wishbone wishbone-bus risc-cpu risc-processor vhdl assembler assembly
Language:Assembly 56
ZipCPU / wbi2c
Wishbone controlled I2C controllers
fpga verilator verilog wishbone-bus i2c-master i2c i2c-slave gplv3
Language:Verilog 38
ZipCPU / s6soc
CMod-S6 SoC
zipcpu fpga fpga-soc verilator wishbone wishbone-bus
Language:Verilog 35
ZipCPU / dbgbus
A collection of debugging busses developed and presented at zipcpu.com
fgpa wishbone-bus wishbone debugging-tools verilator verilog
Language:Verilog 32
ZipCPU / wbfmtx
A wishbone controlled FM transmitter hack
fm-transmitter fpga wishbone wishbone-bus hack verilog verilog-components
Language:Verilog 20
jakubcabal / rmii-firewall-fpga
RMII Firewall FPGA
fpga vhdl firewall rmii ethernet wishbone-bus cyc1000
Language:VHDL 17
ZipCPU / xulalx25soc
A System on a Chip Implementation for the XuLA2-LX25 board
fpga wishbone-bus soc zipcpu
Language:Verilog 15
pbing / ibex_wb
RISC-V Ibex core with Wishbone B4 interface
wishbone wishbone-bus risc-v riscv systemverilog
Language:HTML 12
semahawk / wishbone
Trying to learn Wishbone by implementing few master/slave devices
wishbone wishbone-bus verilog verilog-hdl
Language:SystemVerilog 8
daniel-santos-7 / leaf
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
fpga fpga-soc processor-design risc-v riscv wishbone-bus
Language:VHDL 5
rlee287 / hardware-bus-infrastructure
A collection of formal properties for hardware buses, and cores using them.
bus-standards axi4 psl sva axi4-stream wishbone-bus axi4-lite
Language:Verilog 4
semahawk / icarium
Trying to implement a soft core SoC
verilog verilog-hdl system-on-chip wishbone wishbone-bus softcore soft-core
Language:Verilog 4
pbing / J1_WB
Forth CPU J1 in SystemVerilog and Wishbone interface
systemverilog wishbone-bus wishbone forth-cpu
Language:SystemVerilog 3
cyber-murmel / nmigen-wishbone-examples
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
nmigen nmigen-soc wishbone wishbone-bus fpga fpga-soc
Language:Python 2
zz-systems / Plasma-SoC
Plasma MIPS (I) SoC
cpu de1-soc mips system-on-chip wishbone wishbone-bus zedboard
Language:C 1
Functional-Bus-Description-Language / go-fbdl
Functional Bus Description Language compiler front-end written in Go.
fpga asic axi4 wishbone-bus eda vlsi
Language:Go 0
Functional-Bus-Description-Language / go-vfbdb
Versatile Functional Bus Description Language compiler back-end written in Go.
wishbone-bus fpga asic eda
Language:VHDL 0
pbing / Wishbone
Check Wishbone B4 variants
wishbone wishbone-bus systemverilog
Language:SystemVerilog

wishbone-bus

ZipCPU / zipcpu

ZipCPU / wb2axip

rggen / rggen

ZipCPU / wbuart32

ZipCPU / autofpga

ZipCPU / sdspi

ZipCPU / openarty

jakubcabal / uart-for-fpga

ZipCPU / wbscope

lxp32 / lxp32-cpu

ZipCPU / wbi2c

ZipCPU / s6soc

ZipCPU / dbgbus

ZipCPU / wbfmtx

jakubcabal / rmii-firewall-fpga

ZipCPU / xulalx25soc

pbing / ibex_wb

semahawk / wishbone

daniel-santos-7 / leaf

rlee287 / hardware-bus-infrastructure

semahawk / icarium

pbing / J1_WB

cyber-murmel / nmigen-wishbone-examples

zz-systems / Plasma-SoC

Functional-Bus-Description-Language / go-fbdl

Functional-Bus-Description-Language / go-vfbdb

pbing / Wishbone