uvm-ral-model

There are 2 repositories under uvm-ral-model topic.

rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 427
SystemRDL / PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input
asic eda fpga registers uvm uvm-ral-model uvm-register-model
Language:Python 59
rggen / rggen-sample-testbench
systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl
Language:VHDL 14
kumarrishav14 / arm_watchdog
Verification IP for Watchdog
arm uvm uvm-ral-model watchdog-timer arm-watchdog
Language:SystemVerilog 11
rggen / rggen-sv-ral
UVM RAL class package for RgGen
systemverilog uvm ral uvm-ral-model uvm-register-model
Language:SystemVerilog 6
AlphaLyrae0 / UVM_RAL_DPI_C_Example
Example of C/C++ register access with name through UVM RAL
dpi-c systemverilog uvm uvm-ral-model uvm-register-model verilog
Language:SystemVerilog 3
xver / svdb_gateway
SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.
chipdesign dpi eda hardwareverification ipxact opensource sqlite systemverilog uvm uvm-ral-model asicdesig designverification sql sqlite3
Language:SystemVerilog 3