rvv

There are 2 repositories under rvv topic.

pulp-platform / ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
ara riscv rvv rv64gcv asic cpu vector
Language:C 325
camel-cdr / rvv-bench
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
benchmark risc-v rvv
Language:Assembly 67
ksco / riscv-vector-tests
Unit tests generator for RVV 1.0
generator riscv rvv spike testsuite
Language:Go 41
dzaima / intrinsics-viewer
x86-64, ARM, and RVV intrinsics viewer
avx avx2 avx512 neon risc-v rvv simd-intrinsics sve x86-64
Language:JavaScript 24
jiegec / rvv-kernels
Implements kernels with RISC-V Vector
riscv rvv vector
Language:Assembly 21
camel-cdr / rvv-bench-results
A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
benchmark risc-v rvv
Language:HTML 20
howjmay / neon2rvv
A translator from ARM NEON intrinsics to RISCV-V Extension implementation
aarch64 arm arm64 armv7 armv8 neon riscv riscv64 rvv simd intrinsics
Language:C++ 13
plctlab / riscv-vectorized-benchmark-suite
RISC-V Vectorized Bencmark Suite. based on https://github.com/RALC88/riscv-vectorized-benchmark-suite
risc-v rvv benchmark
Language:C++ 11
dkurt / hair_segmentation
Hair recoloring on RISC-V with OpenCV
deep-learning licheepi mangopi-mq-pro mediapipe opencv risc-v riscv64 tflite rvv
Language:Python 10
UCTECHIP / rocket_chip_vpu
rvv vpu rocket-chip scala chisel
Language:Scala 8
sebikolon / MMM-RVV
MagicMirror² module: Departure monitor for the RVV (Regensburger Verkehrsverbund) bus system (ÖPNV, public transport)
departure-monitor bus transport rvv bayern magicmirror
Language:JavaScript 5
YADRO-KNS / halide_riscv
Examples of Halide language algorithms running on RISC-V
halide llvm risc-v riscv64 rvv vectorization allwinner-d1 c906 xuantie
Language:Assembly 4
cbalint13 / rvv-kernels
RISCV Vector Kernel C/LLVM-IR generator
int8 kernel llvm math riscv rvv tvm vector
Language:C 3
dkurt / llvm-rvv-071
Patched version of LLVM to unblock RISC-V vectorization with 0.7.1 ISA
c906 risc-v rvv
2
MarekPikula / RISC-V-Summit-Europe-2024
Resources for RISC-V Summit Europe 2024 for poster: Accelerating software development for emerging ISA extensions with cloud-based FPGAs: RVV case study
conference risc-v rvv
Language:TeX 1
dkurt / halide_riscv
Examples of Halide language algorithms running on RISC-V
allwinner-d1 c906 halide llvm risc-v riscv64 rvv vectorization xuantie
Language:Assembly 0

rvv

pulp-platform / ara

camel-cdr / rvv-bench

ksco / riscv-vector-tests

dzaima / intrinsics-viewer

jiegec / rvv-kernels

camel-cdr / rvv-bench-results

howjmay / neon2rvv

plctlab / riscv-vectorized-benchmark-suite

dkurt / hair_segmentation

UCTECHIP / rocket_chip_vpu

sebikolon / MMM-RVV

YADRO-KNS / halide_riscv

cbalint13 / rvv-kernels

dkurt / llvm-rvv-071

MarekPikula / RISC-V-Summit-Europe-2024

dkurt / halide_riscv