pulp-platform

common_cells

Common SystemVerilog components

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

pulp_soc

pulp_soc is the core building component of PULP based SoCs

spatz

Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.

common_verification

SystemVerilog modules and classes commonly used for verification

pulp_cluster

The multi-core cluster of a PULP system.

pulp-runtime

Simple runtime for Pulp platforms

snitch_cluster

An energy-efficient RISC-V floating-point compute cluster.

pulp-trainlib

Floating-Point Optimized On-Device Learning Library for the PULP Platform.

svase

cva6

This is the fork of CVA6 intended for PULP development.

hci

Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores

cluster_interconnect

neureka

2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters

redundancy_cells

dram_rtl_sim

obi

regression_tests

ace

astral

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

pulp-ethernet

apb_fll_if

Control interface for FLL

cv32e40x

4 stage, in-order, compute RISC-V core based on the CV32E40P

cva6-sdk

CVA6 SDK containing RISC-V tools and Buildroot

fir-xifu

opentitan

OpenTitan: Open source silicon root of trust

u-boot

Unofficial development fork of U-Boot