pulp-platform

pulp-platform

Geek Repo

Github PK Tool:Github PK Tool

pulp-platform's repositories

pulpissimo

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

Language:SystemVerilogLicense:NOASSERTIONStargazers:342Issues:44Issues:303

mempool

A 256-RISC-V-core system with low-latency access into shared L1 memory.

Language:CLicense:Apache-2.0Stargazers:224Issues:7Issues:7

bender

A dependency management tool for hardware projects.

Language:RustLicense:Apache-2.0Stargazers:197Issues:9Issues:49

cheshire

A minimal Linux-capable 64-bit RISC-V SoC built around CVA6

Language:SystemVerilogLicense:NOASSERTIONStargazers:97Issues:10Issues:11

pulp_soc

pulp_soc is the core building component of PULP based SoCs

Language:SystemVerilogLicense:NOASSERTIONStargazers:66Issues:10Issues:21

FlooNoC

A Fast, Low-Overhead On-chip Network

Language:SystemVerilogLicense:Apache-2.0Stargazers:64Issues:6Issues:2

carfield

A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow on multiple boards is available.

Language:TclLicense:NOASSERTIONStargazers:54Issues:9Issues:32

pulp_cluster

The multi-core cluster of a PULP system.

Language:SystemVerilogLicense:NOASSERTIONStargazers:34Issues:8Issues:3

pulp-runtime

Simple runtime for Pulp platforms

snitch_cluster

An energy-efficient RISC-V floating-point compute cluster.

Language:SystemVerilogLicense:Apache-2.0Stargazers:22Issues:6Issues:26

pulp-trainlib

Floating-Point Optimized On-Device Learning Library for the PULP Platform.

Language:CLicense:Apache-2.0Stargazers:18Issues:5Issues:8

hwpe-stream

IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system

Language:SystemVerilogLicense:NOASSERTIONStargazers:16Issues:8Issues:1
Language:SystemVerilogLicense:NOASSERTIONStargazers:16Issues:5Issues:2

cva6

This is the fork of CVA6 intended for PULP development.

Language:AssemblyLicense:NOASSERTIONStargazers:14Issues:4Issues:1
Language:SystemVerilogLicense:NOASSERTIONStargazers:13Issues:6Issues:6

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Language:SystemVerilogLicense:NOASSERTIONStargazers:13Issues:3Issues:0

hci

Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores

Language:SystemVerilogLicense:NOASSERTIONStargazers:9Issues:5Issues:3
Language:SystemVerilogLicense:NOASSERTIONStargazers:8Issues:7Issues:0
Language:RustLicense:Apache-2.0Stargazers:7Issues:3Issues:6

occamy

A high-efficiency system-on-chip for floating-point compute workloads.

Language:PythonLicense:Apache-2.0Stargazers:6Issues:7Issues:6

astral

A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.

Language:TclLicense:NOASSERTIONStargazers:4Issues:0Issues:0

riscv-isa-sim

Spike, a RISC-V ISA Simulator

Language:CLicense:NOASSERTIONStargazers:4Issues:9Issues:2

archimedes

Architecture for Minimum Energy DNNs at Edge and domain-specific processing(ArchiMEDES)

Language:CLicense:NOASSERTIONStargazers:3Issues:0Issues:0
Language:TclLicense:NOASSERTIONStargazers:2Issues:0Issues:0
Language:SystemVerilogLicense:NOASSERTIONStargazers:2Issues:4Issues:0
Language:SystemVerilogLicense:NOASSERTIONStargazers:1Issues:7Issues:0
Language:CLicense:Apache-2.0Stargazers:1Issues:4Issues:1
Language:SystemVerilogLicense:NOASSERTIONStargazers:0Issues:3Issues:0

opentitan

OpenTitan: Open source silicon root of trust

Language:SystemVerilogLicense:Apache-2.0Stargazers:0Issues:2Issues:0