rtl-design

There are 2 repositories under rtl-design topic.

4xmen / Web-Package-RTL
⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
rtl full-package rtl-package html css rtl-design web-package right-to-left 4xmen xstack persian persian-template components components-and-templates sass rtl-component
Language:HTML 429
pulp-platform / cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
asic fpga riscv rtl-design simulation systemverilog
Language:SystemVerilog 128
4xmen / x-mega-menu
x mega menu is repsonsive mega menu based on vannilajs
4xmen javascript mega-menu menu navbar navigation rtl-design rtl-menu scss vannila-js xstack
Language:JavaScript 114
4xmen / x-tree-select
Tree Select jQuery plugin
rtl-design javascript
Language:JavaScript 60
4xmen / rvnm
Responsive vertical navigation menu
wordpress wordpress-menu wordpress-navigation menu navbar responsive-navbar responsive-menu multi-theme rtl right-to-left rtl-design 4xmen xstack javascript
Language:CSS 58
snbk001 / 100DaysofRTL
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
makefile systemverilog testbench rtl-design verilog synthesis hdl systemverilog-hdl systemverilog-simulation systemverilog-test-bench edge-detector-with-mealy
Language:SystemVerilog 27
Akashtailor-exe / 30-days-of-verilog
30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
30-days-of-code 30daysofcode digital-logic-design digitalcircuit verilog verilog-project vlsi rtl-coding rtl-design verilog-programs
24
gatery
synogate / gatery
Gatery, a library for circuit design.
asic cpp fpga gatery library rtl rtl-design vlsi vlsi-design
Language:C++ 17
maazm007 / 100Daysof_RTL
The Repository contains the code of various Digital Circuits
hdl rtl-design verilog verilog-hdl vlsi-design xilinx-ise
Language:Verilog 8
esynr3z / pip-hdl
📦 Tool to enable package managing for HDL VIP or IP cores (Verilog, SystemVerilog, VHDL) using Python pip
ip-core pip python rtl-design systemverilog verification verilog vhdl vip
Language:Python 5
Luca-Dalmasso / DLX
RTL description, synthesis and physical design of a 4-stage pipelined 32bit RISC processor
vhdl computer-architecture digital-design dlx dlx-instruction-set dlx-processor embedded-systems hardware-designs risc-processor rtl-design
Language:Verilog 4
synogate / gatery_template
Template project for using gatery
asic cpp fpga gatery rtl rtl-design vlsi vlsi-design
Language:C++ 4
alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits
This repository includes all the projects I have done for object-oriented modeling of electronic circuits course at the University of Tehran. In these projects, C++ is used along with SystemC and SystemC-AMS libraries. Spring 2022
gate-level gate-level-simulation image-processing object-oriented object-oriented-programming rtl-design system-modeling systemc systemc-ams
Language:C++ 2
Farbod-Siahkali / Digital-Logical-Designs-Projects
Digital Logical Designs Course Projects
gate-level-simulation rtl state-machine dld-project rtl-design
Language:Verilog 2
Mhd-Shah / Verification-of-D--flipflop-using-UVM
Verification of D-FF using UVM on EDA playground
dflipflop rtl-design systemverilog uvm-verification verilog verilog-hdl
Language:SystemVerilog 2
williaml33moore / bathtub
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic asic-design asic-verification bdd bdd-framework bdd-specs design-verification fpga rtl rtl-design soc-design soc-verification systemverilog uvm uvm-verification verilog verilog-hdl
Language:SystemVerilog 2
Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM
This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.
questasim rtl rtl-design testbench verilog vivado finite-state-machine synthesis systemverilog
Language:Verilog 1
Ammar-Bin-Amir / I2C
RTL Design of Inter-Integrated Circuit
i2c rtl-design serial-communication verilog
Language:Verilog 1
Ammar-Bin-Amir / SPI
RTL Design of Serial Peripheral Interface
rtl-design serial-communication spi verilog
Language:Verilog 1
Ammar-Bin-Amir / UART
RTL Design of Universal Asynchronous Receiver-Transmitter
rtl-design serial-communication uart verilog
Language:Verilog 1
cp024s / 100-days-of-RTL
probable journey of RTL coding ft. Chandra Prakash
fpga-programming systemverilog testbench verilog fpga rtl-design
Language:Verilog 1
gabrielganzer / RTSNoC-Sniffer
Non-intrusive packet delivery monitoring service for Networks-on-Chip (NoCs) focusing on real-time systems. Hardware verification and development in C++/SystemC using the Visual Studio 2017 IDE.
systemc network-on-chip system-on-chip rtl-design computer-architectures c-plus-plus real-time-systems monitoring-tool routing-algorithm
Language:C++ 1
Luca-Dalmasso / Max-Pooling_VHDL
HLSM with memory design for max pooling algorithm.
hardware-designs rtl rtl-design vhdl
Language:VHDL 1
Luca-Dalmasso / RISCV_LBIST
Design of a BIST module for RISC-V fault testing
asic atpg hardware-testing riscv rtl-design tcl vhdl
Language:Verilog 1
sidhantp1906 / AMBA4-APB
Advanced Pheripheral Bus design using verilog HDL
verilog amba-apb amba4 rtl-design protocols digital-system-design
Language:Verilog 1
ZAIN-ALI-02 / UART
An open-source Verilog implementation of UART featuring 8-bit and 32-bit architectures with simulation support for efficient data exchange.
data-transmission rtl-design serial-communication uart verilog asynchronous-transmission serial-communication-protocol testbench-verification
Language:Verilog 1
Ammar-Bin-Amir / ARTY_A7_I2C_BME280
Integration of Arty A7-100T with BME280 Pressure Sensor for Pressure Sensing and FPGA Testing
bme280 i2c pressure-sensor rtl-design artix-7-100t fpga-testing
Language:Verilog 0
Ammar-Bin-Amir / ARTY_A7_I2C_MPU-6050
Integration of Arty A7-100T with MPU-6050 Gyroscope Sensor for Motion Sensing and FPGA Testing
artix-7-100t fpga-testing gyroscope i2c mpu-6050 rtl-design
Language:Verilog 0
Ammar-Bin-Amir / AXI4
RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
axi4 axi4-lite-interface bus-protocol handshaking-algorithm rtl-design verilog
Language:Verilog 0
Ammar-Bin-Amir / RV32I_5-Stage_Pipelined_CPU
Processor Design of RV32I 5-Stage Pipelined CPU
digital-circuit-design risc-v rtl-design rv32i single-cycle-processor 5-stage-pipelined-processor
Language:SystemVerilog 0
Ammar-Bin-Amir / RV32I_Single_Cycle_CPU
Processor Design of RV32I Single Cycle CPU
risc-v rtl-design rv32i single-cycle-processor digital-circuit-design
Language:SystemVerilog 0
diluo1999 / tic_tac_toe
Final project: Tic-tac-toe on VGA monitor. ENGS31/CS56 Digital Electronics @ Dartmouth.
digital-electronics documentation fpga game-development rtl-design tic-tac-toe ui-ux vga vhdl vivado
Language:VHDL 0
farukyld / sort-circuit
an RTL circuit that sorts the integer values in a momory unit connected with (almost) AXI-Lite
axi-lite insertion-sort rtl-design state-machine verilog
Language:Verilog 0
HaaRTLnewbie / 8-bit-CPU
RTL code of an 8-bit CPU designed in Verilog with a separate file for each module.
computer-architecture cpu-architecture rtl-design verilog-hdl learning-by-doing personal-project testbench-verification
Language:Verilog
Shrikantpatil2197 / Project_Build-a-Modern-Computer-from-First-Principles-From-Nand-to-Tetris
Here i develop virtual computer machine starting from Nand gates and finishing at implementing working Tetris game.
operating-system digital-electronics rtl-design programming virtual-machine
tom-zv / FPGA-ESP32-Projects
Projects showcase
embedded fpga-programming rtl-design software-engineering
Language:VHDL

rtl-design

4xmen / Web-Package-RTL

pulp-platform / cheshire

4xmen / x-mega-menu

4xmen / x-tree-select

4xmen / rvnm

snbk001 / 100DaysofRTL

Akashtailor-exe / 30-days-of-verilog

synogate / gatery

maazm007 / 100Daysof_RTL

esynr3z / pip-hdl

Luca-Dalmasso / DLX

synogate / gatery_template

alirezajaberirad / Object-Oriented-Modeling-of-Electronic-Circuits

Farbod-Siahkali / Digital-Logical-Designs-Projects

Mhd-Shah / Verification-of-D--flipflop-using-UVM

williaml33moore / bathtub

Abdelrahman1810 / SPI_Slave_with_Single_Port_RAM

Ammar-Bin-Amir / I2C

Ammar-Bin-Amir / SPI

Ammar-Bin-Amir / UART

cp024s / 100-days-of-RTL

gabrielganzer / RTSNoC-Sniffer

Luca-Dalmasso / Max-Pooling_VHDL

Luca-Dalmasso / RISCV_LBIST

sidhantp1906 / AMBA4-APB

ZAIN-ALI-02 / UART

Ammar-Bin-Amir / ARTY_A7_I2C_BME280

Ammar-Bin-Amir / ARTY_A7_I2C_MPU-6050

Ammar-Bin-Amir / AXI4

Ammar-Bin-Amir / RV32I_5-Stage_Pipelined_CPU

Ammar-Bin-Amir / RV32I_Single_Cycle_CPU

diluo1999 / tic_tac_toe

farukyld / sort-circuit

HaaRTLnewbie / 8-bit-CPU

Shrikantpatil2197 / Project_Build-a-Modern-Computer-from-First-Principles-From-Nand-to-Tetris

tom-zv / FPGA-ESP32-Projects