superscalar

There are 0 repository under superscalar topic.

ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
rocket-chip chip-generator chisel riscv rtl soc peripherals chipyard risc-v boom firesim hwacha accelerators rocket out-of-order superscalar
Language:C 1412
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 762
klessydra / T13x
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
accelerator klessydra mimd pulpino riscv simd superscalar t02x t03x t13x vector-processor
Language:VHDL 42
bcrafton / processor
A compiler, assembler, and processor.
assembler processor memory-simulator compiler superscalar out-of-order branch-predictor performance os simd
Language:OCaml 24
ic-lab-duth / DRIM-S
DUTH RISC-V Superscalar Microprocessor
riscv risc-v systemverilog superscalar processor
Language:SystemVerilog 23
sdasgup3 / parallel-processor-design
Super scalar Processor design
verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler flex bison parallel-computing instruction-level-parallelism mnemonics forwarding bypassing branch-prediction instruction-set opcode
Language:Verilog 20
brunocampos01 / organizacao-e-arquitetura-de-computadores
Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).
ufsc ine5607 multicore superscalar multiprocessor architecture mips32 assembly datapath memory processor semiconductor pipeline-processor principio-da-localidade-memoria cache ine
Language:Assembly 14
SIMDE-ULL / SIMDE
Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals
simulator educational computer-architecture out-of-order computer-architecture-and-organization instruction-level-parallelism learning-by-doing learning-resources pipelining risc superscalar
Language:TypeScript 12
miskcoo / TrivialMIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support
systemverilog cpu superscalar mips
Language:SystemVerilog 9
hibagus / TwoLevelBPSimulator
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
computer-architecture computer-engineering computer-engineering-lab superscalar branch-predictor branch-prediction simulator
Language:C++ 7
markstock / SimdNBodyKernels
Easy-to-implement n-body simulation kernels created using Intel's ispc and llvm/clang
nbody nbody-gravity-simulation superscalar ispc
Language:C++ 5
Applied-Scientific-Research / nvortexVc
Direct Biot-Savart solver for 2D and 3D vortex blobs accelerated with Vc
nbody-simulation vortex-methods superscalar
Language:C++ 4
imalikshake / superscalar
A superscalar processor in Python
architecture processor processor-simulator python superscalar tomasulo
Language:Python 3
mark-i-m / riscy
Superscalar OoO RISCV processor written in Chisel
riscv out-of-order core processor superscalar chisel
Language:Scala 3
Ghonimo / Perceptron-Combinational-Branch-Predictor-SimpleScalar-PSU-ECE587
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
branch-prediction computer-architecture microprocessor perceptron portland-state-university simple-scalar simplescalar-simulator ss3 superscalar superscalar-cpu combinational-branch-prediction perceptron-branch-prediction
Language:C 1
permutationlock / superscalar_processor
Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.
superscalar logisim processor-architecture
Language:Python 1
SSutherlandDeeBristol / superscalar-processor-simulator
A superscalar processor simulator written in Java as part of the Advanced Computer Architecture unit.
processor-simulator superscalar simulator assembly java cpu
Language:Java 0
tomijuarez / ReOrder-Buffer
Out of order superscalar processor simulated in Javascript
hardware processor simulation superscalar
Language:JavaScript