superscalar

There are 1 repository under superscalar topic.

ucb-bar / chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
accelerators boom chip-generator chipyard chisel firesim hwacha out-of-order peripherals risc-v riscv rocket rocket-chip rtl soc superscalar
Language:Scala 1731
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
artix-7 asic branch-prediction coremark cpu fpga in-order linux pipelined-processors risc-v riscv-linux rv32i rv32im superscalar verilator verilog xilinx
Language:Verilog 927
klessydra / T13x
An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
klessydra t13x t03x t02x riscv pulpino superscalar vector-processor accelerator simd mimd
Language:VHDL 45
ic-lab-duth / DRIM-S
DUTH RISC-V Superscalar Microprocessor
riscv risc-v systemverilog superscalar processor
Language:SystemVerilog 29
bcrafton / processor
A compiler, assembler, and processor.
assembler branch-predictor compiler memory-simulator os out-of-order performance processor simd superscalar
Language:OCaml 24
sdasgup3 / parallel-processor-design
Super scalar Processor design
verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler flex bison parallel-computing instruction-level-parallelism mnemonics forwarding bypassing branch-prediction instruction-set opcode
Language:Verilog 21
brunocampos01 / organizacao-e-arquitetura-de-computadores
Repositório para as aulas, exercícios e resumos da matéria: organização e arquitetura de computadores (INE5607).
ufsc ine5607 multicore superscalar multiprocessor architecture mips32 assembly datapath memory processor semiconductor pipeline-processor principio-da-localidade-memoria cache ine
Language:Assembly 18
SIMDE-ULL / SIMDE
Educational computer simulator on a mission to "superscalate" the study of computer architecture fundamentals
simulator educational computer-architecture out-of-order computer-architecture-and-organization instruction-level-parallelism learning-by-doing learning-resources pipelining risc superscalar
Language:TypeScript 13
miskcoo / TrivialMIPS
MIPS32 CPU implemented in SystemVerilog, with superscalar and branch prediction support
cpu mips superscalar systemverilog
Language:SystemVerilog 9
hibagus / TwoLevelBPSimulator
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
computer-architecture computer-engineering computer-engineering-lab superscalar branch-predictor branch-prediction simulator
Language:C++ 8
markstock / SimdNBodyKernels
Easy-to-implement n-body simulation kernels created using Intel's ispc and llvm/clang
nbody nbody-gravity-simulation superscalar ispc
Language:C++ 5
Applied-Scientific-Research / nvortexVc
Direct Biot-Savart solver for 2D and 3D vortex blobs accelerated with Vc
nbody-simulation superscalar vortex-methods
Language:C++ 4
dominiksalvet / super-riscv
Superscalar dual-issue RISC-V processor
risc-v dual-issue in-order open-source superscalar core microarchitecture pipeline rtl systemverilog gtkwave verilator ahb3-lite forwarding low-power riscv-gcc testbench instruction-level-parallelism
Language:SystemVerilog 3
Ghonimo / Perceptron-Combinational-Branch-Predictor-SimpleScalar-PSU-ECE587
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
branch-prediction computer-architecture microprocessor perceptron portland-state-university simple-scalar simplescalar-simulator ss3 superscalar superscalar-cpu combinational-branch-prediction perceptron-branch-prediction
Language:C 3
mark-i-m / riscy
Superscalar OoO RISCV processor written in Chisel
riscv out-of-order core processor superscalar chisel
Language:Scala 3
gitmehrdad / Superscalar-MIPS
This Verilog implementation represents a 32-bit MIPS processor featuring out-of-order execution.
mips mips32 processor-architecture superscalar
Language:Verilog 2
imalikshake / superscalar
A superscalar processor in Python
superscalar processor-simulator tomasulo python processor architecture
Language:Python 2
permutationlock / superscalar_processor
Superscalar 8 bit processor made in logisim and corresponding assembly language to bit code compiler.
superscalar logisim processor-architecture
Language:Python 1
SSutherlandDeeBristol / superscalar-processor-simulator
A superscalar processor simulator written in Java as part of the Advanced Computer Architecture unit.
processor-simulator superscalar simulator assembly java cpu
Language:Java 0
vbogdev / vbn-Riscv
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
axi4 ddr3 fpga out-of-order processor processor-architecture processor-design processor-simulator risc-v superscalar superscalar-cpu
Language:SystemVerilog 0
tomijuarez / ReOrder-Buffer
Out of order superscalar processor simulated in Javascript
superscalar processor hardware simulation
Language:JavaScript
YconquestY / ooo470
CS-470 Homework 1
dynamic-scheduling mips-r10000 ooo processor-simulator superscalar
Language:Python