UC Berkeley Architecture Research

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

gemmini

Berkeley's Spatial Array Generator

riscv-sodor

educational microarchitectures for risc-v isa

berkeley-hardfloat

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

constellation

A Chisel RTL generator for network-on-chip interconnects

saturn-vectors

Chisel RISC-V Vector 1.0 Implementation

uciedigital

Pure digital components of a UCIe controller

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

Baremetal-NN

Tool for converting PyTorch models into raw C codes with minimal dependency and some performance optimizations.

cva6-wrapper

Wrapper for ETH Ariane Core

nvdla-wrapper

Wraps the NVDLA project for Chipyard integration

autocomp

compress-acc

radiance

Rocket Chip Generator

FFTGenerator

Accelerated-TinyMPC

Model-predictive control for microcontrollers (fork mapping tinyMPC to gemmini or other HW accelerators)

stac-top

The SRAM timing analysis chip for verifying SRAMs generated by SRAM22

ibex-wrapper

Wrapper for lowRISC Ibex

ara-wrapper

caliptra-aes-acc

mempress

uciephytest

vexiiriscv-tile

Chisel wrapper for the SpinalHDL VexiiRiscv CPU implementation, implementing Chipyard compatibility

sp24-Baremetal-IDE

A submodule of Chipyard https://github.com/ucb-bar/chipyard

SteamVR-Bridge

Codebase used for Berkeley Humanoid Lite teleoperation demonstration.

zephyr-chipyard-sw

IsaacLab

Unified framework for robot learning built on NVIDIA Isaac Sim

xrsight

A hardware–software co-design framework for developing and characterizing extended reality (XR) workloads on embedded systems-on-chip (SoCs).

zephyr

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.