UC Berkeley Architecture Research

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

gemmini

Berkeley's Spatial Array Generator

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

berkeley-hardfloat

hammer

Hammer: Highly Agile Masks Made Effortlessly from RTL

chiseltest

The batteries-included testing and formal verification library for Chisel-based RTL designs.

testchipip

gemmini-rocc-tests

Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator

RoSE

A unified simulation platform that combines hardware and software, enabling pre-silicon, full-stack, closed-loop evaluation of your robotic system.

nvdla-wrapper

Wraps the NVDLA project for Chipyard integration

shuttle

A Rocket-based RISC-V superscalar in-order core

rocket-dsp-utils

Tools for integrating DspTools components into a rocket-chip

FFTGenerator

riscv-tools-feedstock

spike-devices

Collection of device models for spike

Accelerated-TinyMPC

Model-predictive control for microcontrollers (fork mapping tinyMPC to gemmini or other HW accelerators)

Baremetal-IDE

A submodule of Chipyard https://github.com/ucb-bar/chipyard

chipyard-cs152-sp24

stac-bringup

Bringup infrastructure for the SRAM Timing Analysis Chip

tsi

Standalone tethered serial interface (TSI) implementation with CLI utilities.

AuRORA

Virtualized Accelerator Orchestration for Multi-Tenant Workloads

Baremetal-IDE-bsp

Parent Repo: https://github.com/ucb-bar/Baremetal-IDE

darecreek

Fork of Intel's DareCreek Vector Unit

dsp-blocks

A collection of common Digital Signal Processing block generators

radiance

Rocket Chip Generator

riskybear-firmware

riskybear-mechanical

rocc-acc-utils

rocket-pcb

PCB libraries and templates for rocket-chip based FPGA/ASIC designs

sdf-fft

A Single-path Delay Feedback FFT Generator