Professur für VLSI-Entwurfssysteme, Diagnostik und Architektur

Professur für VLSI-Entwurfssysteme, Diagnostik und Architektur's repositories

PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Language:VHDLNOASSERTION523 58 54

PoC-Examples

This repository contains synthesizable examples which use the PoC-Library.

Language:VHDLApache-2.032 10 1

RC2F

Reconfigurable Common Computing Framework (RC2F)

NOASSERTION4 60

RC3E

Reconfigurable Common Cloud Computing Environment (RC3E)

NOASSERTION4 60

UVVM

Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.

Language:VHDLMIT4 60

OSVVM

Open Source VHDL Verification Methodology (OSVVM) Repository

Language:VHDL3 50

rc3e-client

Client software for RC3E.

NOASSERTION2 60

rc3e-node

The RC3E Node.

NOASSERTION2 60

rc3e-server

The RC3E Server (resource manager).

NOASSERTION2 60

vunit

VUnit is a unit testing framework for VHDL

Language:VHDLNOASSERTION2 50

cocotb

Coroutine Co-simulation Test Bench

Language:PythonNOASSERTION1 50

pyIPCMI

A Python-based IP Core Management Infrastructure.

Language:PythonNOASSERTION1 60

rc3e-manager

A django-based web application for managing your rc3e installation

Language:PythonGPL-3.0060

sphinx_rtd_theme

Sphinx theme for readthedocs.org

Language:CSSMIT050