branch-prediction

There are 2 repositories under branch-prediction topic.

segmentio / asm
Go library providing algorithms optimized to leverage the characteristics of modern CPUs
go golang assembly avo simd assembler x86 arm branch-prediction
Language:Go 845
ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 764
mipt-mips
MIPT-ILab / mipt-mips
Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs
mips cpu cpu-cache clock-precise branch-prediction branch-predictor computer-architecture-lesson computer-architecture pre-silicon mips-binutils mipt simulator cpu-model risc simulation prediction-algorithms optimizations risc-v pipeline
Language:C++ 328
skyzh / RISCV-Simulator
💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visualization. Project report available.
riscv riscv32 riscv-emulator cpp cmake gtest speculation riscv-simulator cpu pipeline tomasulo-algorithm branch-prediction computer-architecture
Language:C++ 180
sifferman / labs-with-cva6
Advanced Architecture Labs with CVA6
branch-prediction caching cva6 education out-of-order risc-v systemverilog virtual-memory
Language:SystemVerilog 35
sdasgup3 / parallel-processor-design
Super scalar Processor design
verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler flex bison parallel-computing instruction-level-parallelism mnemonics forwarding bypassing branch-prediction instruction-set opcode
Language:Verilog 20
yonseicasl / Kite
Kite: Architecture Simulator for RISC-V Instruction Set
risc-v simulator architecture five-stage pipeline model education assembly computer-architecture microarchitecture pipelining branch-prediction cache instruction-set instruction-set-architecture memory instruction-dependency
Language:C++ 13
saivittalb / branch-prediction-programming
🎞 Implementation of several Branch Prediction algorithms and analysis on their effectiveness on real-world program traces.
branch-prediction python computer-architechure cpp visual-studio-code
Language:C++ 11
rauhul / ece411
Computer Architecture UIUC SP 2018
cpu-design lc3 branch-prediction cache
Language:Assembly 9
snie2012 / computer-architecture-projects
Computer architecture related projects
computer-architecture branch-prediction cache-simulator dynamic-schedule
Language:C++ 9
ethanelle / Branch-Predictors
A branch predictor simulator in C++ that tests 6 different types of branch predictors.
cpp branch-prediction
Language:C++ 8
hibagus / TwoLevelBPSimulator
Two Level Branch Predictor Simulator - EE382N Superscalar Microprocessor Architecture, Spring 2019, Assignment 4
computer-architecture computer-engineering computer-engineering-lab superscalar branch-predictor branch-prediction simulator
Language:C++ 7
maxislash / branchPredictor
VHDL code of three branch predictors
vhdl branch-predictor branch-prediction computer-architecture computer-engineering
Language:VHDL 6
artem0 / benchmarking
System benchmarks over JVM with JMH - SIMD (superscalar processing), Branch prediction, False sharing.
java jmh jmh-benchmarks benchmarking java-benchmarks benchmark simd simd-parallelism branch-prediction jvm jvm-metrics simd-benchmark simd-operation transformations java-memory-model
Language:Java 5
Gripnook / mips-pipelined-processor
A pipelined implementation of a MIPS processor that was optimized to use data forwarding, caching and branch prediction.
mips-processor pipelining forwarding caching branch-prediction
Language:VHDL 4
hakula139 / MIPS-CPU
A MIPS processor with Cache and Advanced Branch Predictor written in SystemVerilog
mips-processor systemverilog cache branch-prediction pipeline
Language:SystemVerilog 4
csbanon / branch-predictor
Branch Predictor is a C# program that runs a gshare branch prediction simulation, according to a specified number of Global Buffer Table (GBT) and Global History Record (GHR) bits. 2019.
branch-prediction branch-predictor gbt ghr global-branch-predictor global-buffer-table globar-history-record gshare gshare-table
Language:C# 3
hagary / processor-simulator
A superscalar out-of‐order architectural simulator (With Memory Hierarchy).
processor memory-hierarchy processor-simulator object-oriented java tomasulo registers microprocessor branch-prediction speculation
Language:Java 3
rishiraj824 / branch-predictor
2 bit saturated branch predictor with BHR (Branch History Register)
branch-prediction mips computer-architecture
Language:C++ 3
0mega28 / CPU-Simulator
CENOS: The Modern CPU Simulator
cpu-simulation out-of-order scoreboarding-algorithm pipeline-processor 2-pass-assembler branch-prediction simulator
Language:C++ 2
szabolor / branch-prediction
Playing with branch-prediction and simulation
branch-prediction
Language:C 2
Arash1381-y / branch-predictor-simulator
Educational project aimed at evaluating the effectiveness of different correlating branch predictors on benchmarks
branch-prediction branch-predictor simulator yeh-and-patt-classification
Language:Java 1
ChufanSuki / mips_cpu
My Computer Architecture Course Project in CQU
computer-architecture chongqing-university cqu pipeline branch-prediction cache
Language:SystemVerilog 1
cwang360 / branch-prediction-visualization
Tool for visualizing and comparing different dynamic branch prediction methods for a pipelined processor.
branch-prediction computer-architecture
Language:Python 1
DiamonDinoia / cpu-performance-tests
This repository contains the code to benchmark CPU cache miss latency and branch misprediction penalty
cpp hpc branch-prediction memory-latency cache-latency branchless
Language:Jupyter Notebook 1
electricsquare / chip-history
talk hardware-architectures cpu cisc risc pipeline branch-prediction cache multi-core
Language:JavaScript 1
Ghonimo / Perceptron-Combinational-Branch-Predictor-SimpleScalar-PSU-ECE587
Implementation of advanced branch predictors, including Perceptron and Combinational Two-Level Adaptive Predictors, within the SimpleScalar simulator. Showcases enhancements in prediction accuracy and dynamic branch prediction techniques. This is a project for PSU ECE 587: Advanced Computer Architecture
branch-prediction computer-architecture microprocessor perceptron portland-state-university simple-scalar simplescalar-simulator ss3 superscalar superscalar-cpu combinational-branch-prediction perceptron-branch-prediction
Language:C 1
ivanbgd / Branch_Prediction
Compares execution speed of processing sorted and unsorted arrays, with and without branching. Disassembly and results included.
c-plus-plus cplusplus cpp branch-prediction
Language:C++ 1
liuly0322 / riscv32-ustc-codh-lab6
USTC 2022 春季学期 CODH 课程综合实验
branch-prediction cpu pipeline risc-v rv32i vga
Language:Verilog 1
MIPT-ILab / PipelineFlowchartVis
MIPT-V Pipeline Flowchart Visualizer
simulator cpu pipeline mips simulation mipt cpu-cache optimizations computer-architecture risc cpu-model risc-v branch-prediction computer-architecture-lesson branch-predictor clock-precise cycle-accurate pre-silicon prediction-algorithm
Language:CSS 1
MuAlphaOmegaEpsilon / BranchHinting
C++ Macro definitions for easy branch hinting.
cpp branch-prediction branch-predictor static-branch-prediction macros gcc clang icc msvc cross cpp-library library cmake make makefile doxygen doxygen-documentation
Language:C++ 1
murattokez / gshare-gem5
gshare branch prediction implemantaion on gem5
branch-prediction gem5 gem5-simulator gshare
Language:C++ 1
splAcharya / Simulate_Branch_Prediction
Implemented an algorithm to simulate the use of dynamic branch prediction schemes
computer-architecture branch-prediction cpp
Language:C++ 1
tommythorn / bp
Fun with branch predictors
microarchitecture branch-prediction rust-lang yags gshare
Language:Rust 1
YutingJiang / CSE240A
Implementation of 4 different branch predictors in C
branch-prediction gshare tournament static-branch-prediction
Language:C 1
kushrm2803 / RISC-V_Assembler
Simple RISC-V assembler program based on Venus that converts RISC-V assembly language (.asm) into machine language (.mc) format.
assembly risc-v venus branch-prediction
Language:Assembly

branch-prediction

segmentio / asm

ultraembedded / biriscv

MIPT-ILab / mipt-mips

skyzh / RISCV-Simulator

sifferman / labs-with-cva6

sdasgup3 / parallel-processor-design

yonseicasl / Kite

saivittalb / branch-prediction-programming

rauhul / ece411

snie2012 / computer-architecture-projects

ethanelle / Branch-Predictors

hibagus / TwoLevelBPSimulator

maxislash / branchPredictor

artem0 / benchmarking

Gripnook / mips-pipelined-processor

hakula139 / MIPS-CPU

csbanon / branch-predictor

hagary / processor-simulator

rishiraj824 / branch-predictor

0mega28 / CPU-Simulator

szabolor / branch-prediction

Arash1381-y / branch-predictor-simulator

ChufanSuki / mips_cpu

cwang360 / branch-prediction-visualization

DiamonDinoia / cpu-performance-tests

electricsquare / chip-history

Ghonimo / Perceptron-Combinational-Branch-Predictor-SimpleScalar-PSU-ECE587

ivanbgd / Branch_Prediction

liuly0322 / riscv32-ustc-codh-lab6

MIPT-ILab / PipelineFlowchartVis

MuAlphaOmegaEpsilon / BranchHinting

murattokez / gshare-gem5

splAcharya / Simulate_Branch_Prediction

tommythorn / bp

YutingJiang / CSE240A

kushrm2803 / RISC-V_Assembler