quartus

There are 1 repository under quartus topic.

hdl-util / hdmi
Send video/audio over HDMI on an FPGA
hdmi fpga dvi audio video systemverilog hdlmake quartus altera xilinx intel vivado
Language:SystemVerilog 1212
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 283
PyFPGA / pyfpga
A Python package to use FPGA development tools programmatically.
fpga python tcl ghdl ise libero quartus vivado yosys nextpnr icestorm trellis diamond
Language:Python 141
hell03end / verilog-uart
Simple 8-bit UART realization on Verilog HDL.
verilog hdl quartus uart fpga
Language:Verilog 110
hdl-util / sdram-controller
Generic FPGA SDRAM controller, originally made for AS4C4M16SA
sdram dram controller systemverilog as4c4m16sa fpga quartus
Language:Verilog 81
halfmanhalftaco / fpga-docker
Tools for running FPGA vendor toolchains with Docker
fpga verilog vhdl quartus altera xilinx lattice
Language:Makefile 77
CTSRD-CHERI / quartus-install
Install Intel FPGA 'Quartus Prime' software on remote servers
quartus quartus-prime fpga
Language:Python 61
RomeoMe5 / DDLM
Исходные коды к главам книги "Цифровой синтез: практический курс" (под ред. А.Ю. Романова и Ю.В. Панчула)
ddlm verilog labs terasic-de10-lite terasic hse miem schoolmips mips mips-architecture verilog-designs fsm alu quartus modelsim dmk-press verilog-book system-verilog tcl quartus-prime
Language:Verilog 61
MJoergen / HyperRAM
Portable HyperRAM controller
hyperram xilinx vivado artix fpga vhdl avalon intel altera lattice quartus modelsim questasim questa
Language:VHDL 60
nhasbun / de10nano_vgaHdmi_chip
Test for video output using the ADV7513 chip on a de10 nano board
fpga de10nano arm vga hdmi quartus verilog video terasic-de1-soc
Language:Verilog 55
sdk-docker-fpga
raetro / sdk-docker-fpga
Intel Quartus Prime Synthesis Engine for Docker
ci-cd cyclone-10lp cyclone-iii cyclone-iv cyclone-v docker fpga fpga-programming fpga-soc intel jtag max10 mimic mist mister quartus sidi workflow
Language:Dockerfile 51
tymonx / virtio
Virtio implementation in SystemVerilog
verilog systemverilog hdl rtl cmake verilator virtio quartus fpga xilinx vivado model systemc
Language:SystemVerilog 47
mbtaylor1982 / ReSDMAC
Verilog code to replace the Commodore SDMAC found in the A3000
amiga amiga-hardware open-source verilog kicad altera-fpga intel-fpga quartus
Language:Verilog 43
VHDL / PoC
IP Core Library - Published and maintained by the Open Source VHDL Group
altera asic collection diamond fpga ghdl hdl ipcore library nvc quartus synthesis verification vhdl vivado xilinx
Language:VHDL 40
sevvalmehder / 32-bit-MIPS-Processor
A 32-bit MIPS processor used Altera Quartus II with Verilog.
mips register opcodes datapath processor altera quartus
Language:Verilog 28
tow3rs / jtag-mpsse-blaster
Use an MPSSE FTDI device as a JTAG interface in Quartus tools
blaster ft2232h ft232h ft4232h jtag mpsse quartus ft2232d
Language:C 27
baioc / quartus-linux
Quartus II installation tutorial for Debian-based Linux distros
quartus tutorial debian ubuntu ufsc
26
FFT
Jefferson-Lopes / FFT
FFT algorithm for fpga
fft fft-algorithm fpga python quartus verilog
Language:Verilog 23
GSimas / INE5406
📚Repositório da Disciplina INE5406 - Sistemas Digitais
sistemas digitais ine5406 quartus vhdl rtl fpga eda digital-systems circuits electrical-engineering electronic design automation hardware-description-language ufsc
Language:HTML 20
maxs-well / USB_Ctrl
USB2.0 Verilog
usb verilog usb2 cy7c68013a altera cyclone quartus
Language:Verilog 19
xThaid / fpga-lb
A toy L4 load balancer running on FPGA
fpga networking quartus freertos hardcaml ocaml vexriscv verilator load-balancer dataflow riscv
Language:C 18
MaorAssayag / Architecture-of-CPU-projects
VHDL , ModelSIM, Quartus, FPGA, Image Processing
vhdl cpu-architecture modelsim quartus fpga
Language:VHDL 17
Amirarsalan-sn / RISCV-multi-cycle-processor
A multi-cycle processor designed according to the instruction set(assembly language) of RISC-V using the System Verilog HDL
cpu hardware hdl modelsim multi-cycle-processor quartus risc risc-v system-verilog
Language:SystemVerilog 16
Goshik92 / multicore-nios
Matrix multiplication on multiple Nios II cores
quartus nios nios2 verilog hdl sopc fpga fpga-soc de2-115 parallel-computing parallel-programming spmd mailbox shared-memory qsys platform-designer matrix-multiplication
Language:C 16
obiwanjacobi / Zalt
Zalt is a home brew Z80 computer with a modern(isch) chipset.
z80 psoc5lp cpld kicad c z80asm wincupl quartus altera
Language:C 16
Elphel / vdt-plugin
mirror of https://git.elphel.com/Elphel/vdt-plugin
verilog eclipse ide vivado quartus icarus-verilog cocotb gtkwave eclipse-plugin
Language:Java 15
alvarezpj / single-cycle-cpu
VHDL implementation of a 1 Hz single cycle CPU that supports recursive function calls
vhdl single-cycle fpga quartus altera-fpga de2-board
Language:VHDL 14
baleinesurseine / macOsQuartus
Dockerize altera's Quartus ii software and run it on macOS
quartus macos docker-container x11 xquartz modelsim
Language:Dockerfile 13
miscellaneousbits / DE10_NANO_SOC_MINIMAL
SHA3-256 MINER CORE
fpga miner cyclone verilog sha3 sha3-256 cyclone-v quartus de10 de10-nano keccak keccak-256 socfpga
Language:C 13
vmunoz82 / quartus13
EDA Tools: Altera Quartus 13 Dockerfile
eda quartus altera dockerfile fpga
Language:C 13
avestura / PingPongGame_CAD_VGA
🏓 A Ping Pong game written in VHDL with VGA support
vhdl hardware cad university guilan-university vga quartus intel computer-aided-design game ping-pong ping-pong-game
Language:VHDL 12
Charlie5DH / RISC-V-Single-Cycle-uP
Design and implementation in VHDL for FPGAs of a single cycle RISC-V based architecture
vhdl risc-v microprocessors vhdl-code fpga quartus
Language:VHDL 12
mishakevlishvili / fpga_riscv_cpu
fpga verilog risc-v rv32i cpu
risc-v riscv fpga-soc fpga-risc-v verilog rv32i rom-execution fpga altera quartus
Language:Verilog 12
powerplayer9 / Voice-Based-Motor-Control
A verilog HDL based project to control a servomotor with voice commands from an android phone.
verilog-project verilog-hdl servo-motor quartus de10-nano bluetooth terasic-rfs motor-controller voice-commands
Language:Verilog 12
rodrigomelo9 / verifying-foss-hdl-synthesizers
a project to check the FOSS synthesizers against vendors EDA tools
yosys ghdl ghdl-yosys-plugin foss-synthesizers pyfpga ise vivado quartus iverilog verilator
Language:Makefile 12
jonpalmisc / usb_blaster_arm64
Altera USB Blaster drivers for Windows 11 Arm
altera fpga quartus
Language:Shell 11

quartus

hdl-util / hdmi

tymonx / logic

PyFPGA / pyfpga

hell03end / verilog-uart

hdl-util / sdram-controller

halfmanhalftaco / fpga-docker

CTSRD-CHERI / quartus-install

RomeoMe5 / DDLM

MJoergen / HyperRAM

nhasbun / de10nano_vgaHdmi_chip

raetro / sdk-docker-fpga

tymonx / virtio

mbtaylor1982 / ReSDMAC

VHDL / PoC

sevvalmehder / 32-bit-MIPS-Processor

tow3rs / jtag-mpsse-blaster

baioc / quartus-linux

Jefferson-Lopes / FFT

GSimas / INE5406

maxs-well / USB_Ctrl

xThaid / fpga-lb

MaorAssayag / Architecture-of-CPU-projects

Amirarsalan-sn / RISCV-multi-cycle-processor

Goshik92 / multicore-nios

obiwanjacobi / Zalt

Elphel / vdt-plugin

alvarezpj / single-cycle-cpu

baleinesurseine / macOsQuartus

miscellaneousbits / DE10_NANO_SOC_MINIMAL

vmunoz82 / quartus13

avestura / PingPongGame_CAD_VGA

Charlie5DH / RISC-V-Single-Cycle-uP

mishakevlishvili / fpga_riscv_cpu

powerplayer9 / Voice-Based-Motor-Control

rodrigomelo9 / verifying-foss-hdl-synthesizers

jonpalmisc / usb_blaster_arm64