pipelined-processors

There are 0 repository under pipelined-processors topic.

ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 764
ZeyadTarekk / RISC-Pipelined-Processor
5 stages RISC pipelined processor following Harvard architecture.
computer-architecture hdl pipeline pipelined-processors pipelined-risc risk verilog
Language:Verilog 8
EmanOthman21 / MIPS-Pipelined-Processor
This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.
assembler computer-architecture mips mips-architecture pipelined-processors vhdl
Language:VHDL 7
Matrixpecker / VE370-Pipelined-Processor
An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.
computer-organisation-architechure cpu hazard-detection pipeline pipelined-processors
Language:Verilog 7
JunnanLi / TuMan
A Pipelined RISC-V Core
fpga verilog riscv pipelined-processors
Language:Verilog 6
abdullahalshawafi / RISC-Processor
A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA. There are eight 2-byte general-purpose registers, and another three special-purpose registers (Program Counter, Exception Program Counter, Stack Pointer). The memory address space is 1 MB of 16-bit width and is word addressable.
processor computer-architecture vhdl pipelined-processors
Language:VHDL 5
avikram2 / RISCVPipelinedProcessor
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
cache pipelined-processors pipelined-risc riscv32 set-associative-cache victim-cache
Language:Verilog 5
fardinabbasi / RISC-V_Processor_Pipelined
Digital Systems 2 Course [ECE 778] - CA4 - Spring 2023 - University of Tehran - Dr. Safari
computer-architecture computer-arithmetic digital-systems modelsim pipelined-processors risc-v verilog
Language:Verilog 4
Elzawawy / mips-processor-simulator
A simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
mips mips-architecture mips-simulator single-cycle-processor multi-cycle-processor pipelined-processors
Language:SystemVerilog 3
naderabdalghani / 32-bit-risc-pipelined-processor
Implementation of a simple 5-stage 32-bit pipelined processor and its assembler using VHDL and Python
hardware cpu-design 32-bit pipelined-processors assembler-implementation
Language:VHDL 3
Sanskar777 / Dynamic-branch-predictor-in-pipelined-processors
verilog-hdl branch-predictor pipelined-processors
Language:Verilog 3
AbdelrahmanHamdyy / RISC-Pipelined-Processor
5 stages RISC pipelined processor with multiple instructions implemented in verilog including ALU Operations, Interrupts as a state machine, Jumps and branching instructions, Memory operations and more.. following Harvard architecture.
alu-digital-circuit assembler computer-architecture hazards interrupts memory pipelined-processors systemverilog verilog
Language:SystemVerilog 2
abdulkhan94 / Computer-Design-and-Prototyping
MIPS 32 bit processor - fully functional shared memory dual-core processor with MSI for cache coherency
pipelined-processors cache-coherency multicore
Language:SystemVerilog 2
akankshac-073 / MIPS-5-stage-pipelined-control-and-datapath
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.
computer-architecture mips-processor pipelined-processors verilog mips-architecture mips-pipline-processor-verilog mips32
Language:Verilog 2
sts08015 / risc-v-lab
Extended Version of COSE222 Lab
pipelined-processors risc-v single-cycle-processor systemverilog verilog
Language:SystemVerilog 2
AhsanAliUet / riscv-3-stage-pipelined-processor-core
Fully implemented 3 staged pipelined RISC-V processor with hazard detection unit. Hazard detection unit solves the hazards by stalling and forwarding technique. CSR and MRET Instructions are also supported as they can configure and manage all the interrupt/exceptions.
3-stage-pipelined-riscv csr interrupts pipelined-processors riscv
Language:SystemVerilog 1
Cambrian34 / Cs-385-Semester-Project
16-bit 5 stage pipelined Mips processor
16-bit mips pipelined-processors project risc-v verilog
Language:Verilog 1
ce-box / CE4302-vector-processor
Vector ASIP for the application of filters to an image 🖼️
computer-architecture fpga pipelined-processors vector-processor vhdl
Language:SystemVerilog 1
fsiddiqui85 / IPPro
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
datapath fpga hardware-acceleration image-processing microprocessor pipelined-processors processor risc softcore xilinx-zynq ippro
Language:Verilog 1
MaheenAnees / Single-Cycle-RISCV-Processor
This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.
risc-v pipelined-processors single-cycle-processor computer-architecture verilog
Language:Verilog 1
muhammad-sayed-mahdy / pipelined-processor
5-stage pipelined microprocessor with data forwarding, hazard detection and dynamic branch prediction written in VHDL
cpu hardware microprocessor pipelined-processors vhdl
Language:VHDL 1
anasdeis / MIPS-Pipelined-Processor
Standard five-stage pipelined 32-bit MIPS processor with hazard detection
vhdl pipelined-processors mips-architecture
Language:VHDL 0
Chaosinflesh / tagged-branch-predictor
Investigating the use of hint bits in JUMP statements for pipelined CPU branch predictors
branch-prediction code-optimization high-performance-computing pipelined-processors
0
meeeeet / 5-Stage-Pipelined-RISC-V-Processor
pipelined-processors risc-processor risc-v rv32i
Language:Verilog 0
bori00 / DataForwardingMIPS
hazard-detection pipelined-processors risc
Language:VHDL
bori00 / StalledMIPS
Structure of Computer Systems course (3rd year, 1st semester)
hazard-detection pipelined-processors risc
Language:VHDL
bori00 / TomasuloAlgorithm
concurrency hazard-detection pipelined-processors tomasulo-algorithm
Language:VHDL
sarthakmittal92 / risc-proc
Repository for the course project done as part of CS-230 (Digital Logic Design & Computer Architecture) course at IIT Bombay in Spring 2022.
pipelined-processors processor-architecture quartus risc vhdl
Language:VHDL
tylerfeldman321 / Crane-Game
Crane Game using Custom Pipelined Processor
3d-printing arduino assembly-language circuit-design laser-cutting mechanical-engineering pipelined-processors stepper-motor-control verilog-hdl
Language:VHDL
valerii-martell / Pipelined-Calculators-FPGA
A set of pipelined calculators for computing various complex mathematical functions
fpga vhdl pipeline pipelined-processors
Language:VHDL

pipelined-processors

ultraembedded / biriscv

ZeyadTarekk / RISC-Pipelined-Processor

EmanOthman21 / MIPS-Pipelined-Processor

Matrixpecker / VE370-Pipelined-Processor

JunnanLi / TuMan

abdullahalshawafi / RISC-Processor

avikram2 / RISCVPipelinedProcessor

fardinabbasi / RISC-V_Processor_Pipelined

Elzawawy / mips-processor-simulator

naderabdalghani / 32-bit-risc-pipelined-processor

Sanskar777 / Dynamic-branch-predictor-in-pipelined-processors

AbdelrahmanHamdyy / RISC-Pipelined-Processor

abdulkhan94 / Computer-Design-and-Prototyping

akankshac-073 / MIPS-5-stage-pipelined-control-and-datapath

sts08015 / risc-v-lab

AhsanAliUet / riscv-3-stage-pipelined-processor-core

Cambrian34 / Cs-385-Semester-Project

ce-box / CE4302-vector-processor

fsiddiqui85 / IPPro

MaheenAnees / Single-Cycle-RISCV-Processor

muhammad-sayed-mahdy / pipelined-processor

anasdeis / MIPS-Pipelined-Processor

Chaosinflesh / tagged-branch-predictor

meeeeet / 5-Stage-Pipelined-RISC-V-Processor

bori00 / DataForwardingMIPS

bori00 / StalledMIPS

bori00 / TomasuloAlgorithm

sarthakmittal92 / risc-proc

tylerfeldman321 / Crane-Game

valerii-martell / Pipelined-Calculators-FPGA