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Micro Architecture at Santa Cruz (MASC) (masc-ucsc)

Micro Architecture at Santa Cruz (MASC)

masc-ucsc

Geek Repo

Location:UC Santa Cruz

Home Page:http://masc.soe.ucsc.edu/

Github PK Tool:Github PK Tool

Micro Architecture at Santa Cruz (MASC)'s repositories

livehd

Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

Language:VerilogLicense:NOASSERTIONStargazers:201Issues:28Issues:179

esesc

ESESC: A Fast Multicore Simulator

Language:CStargazers:131Issues:32Issues:16

hdlagent

LLM Agent for Hardware Description Language

Language:PythonLicense:Apache-2.0Stargazers:9Issues:19Issues:1

hif

Hardware Interchange Format

Language:C++License:NOASSERTIONStargazers:8Issues:19Issues:1

MASC-AI-Synthesized-Cryptoprocessor

Language:VerilogLicense:Apache-2.0Stargazers:5Issues:4Issues:0

pyrope_artifacts

Pyrope, a modern HDL with a Live flow

Language:CLicense:BSD-3-ClauseStargazers:5Issues:20Issues:89

livehd_regression

LiveHD Regression suite and scripts

Language:VerilogLicense:Apache-2.0Stargazers:3Issues:20Issues:0

mmm

Memory Marionette Model

Language:C++License:Apache-2.0Stargazers:3Issues:18Issues:1

tree-sitter-pyrope

tree-sitter Pyrope grammar

Language:CLicense:BSD-3-ClauseStargazers:3Issues:19Issues:1

desesc

Dromajo ESESC

Language:C++License:Apache-2.0Stargazers:2Issues:18Issues:1

dromajo

RISC-V RV64GC emulator designed for RTL co-simulation

Language:C++License:Apache-2.0Stargazers:1Issues:2Issues:0

hdeval

Hardware Description Language Evaluation suite for LLM

Language:ShellLicense:GPL-3.0Stargazers:1Issues:17Issues:0

hhds

Hardware Hierarchical Dynamic Structures

Language:C++License:Apache-2.0Stargazers:1Issues:17Issues:1

superbp

Super Scalar Branch Predictor

Language:C++License:NOASSERTIONStargazers:1Issues:21Issues:0

airspace-hugo

Airspace theme (Hugo version)

Language:CSSLicense:MITStargazers:0Issues:2Issues:0

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

Language:SystemVerilogLicense:NOASSERTIONStargazers:0Issues:2Issues:0

bazel_rules_hdl

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

Language:StarlarkLicense:Apache-2.0Stargazers:0Issues:1Issues:0

black-parrot

A Linux-capable RISC-V multicore for and by the world

Language:SystemVerilogLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

black-parrot-sdk

Language:PythonLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

black-parrot-sim

Language:DockerfileLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Language:CLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

docs

Documentation for LiveHD and Pyrope

Language:RubyLicense:Apache-2.0Stargazers:0Issues:20Issues:0

hlop

Hardware Logic Operation Library

Language:C++License:Apache-2.0Stargazers:0Issues:18Issues:1

libelf

Fork from https://web.archive.org/web/20181111033959/www.mr511.de/software/libelf-0.8.13.tar.gz (needed by dromajo)

Language:CLicense:LGPL-2.1Stargazers:0Issues:3Issues:0

madaweb

HSC Website

Language:HTMLLicense:Apache-2.0Stargazers:0Issues:26Issues:0

OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

Language:VerilogLicense:NOASSERTIONStargazers:0Issues:1Issues:0

riscv-boom

SonicBOOM: The Berkeley Out-of-Order Machine

Language:ScalaLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

slang

SystemVerilog compiler and language services

Language:C++License:MITStargazers:0Issues:1Issues:0

termwave

Terminal Digital Electronics Wave viewer library

Language:C++License:Apache-2.0Stargazers:0Issues:20Issues:0

udsim

User Design Simulator

Language:CLicense:MITStargazers:0Issues:4Issues:0