pnr

There are 0 repository under pnr topic.

efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
asic drc eda flows gdsii gf180mcu lvs openlane openroad pdk pnr silicon sky130 sta verilog vlsi rtl-to-gds flow
Language:Python 172
US-CBP / GTAS
Global Travel Assessment System | A passenger data screening and analysis system for enhancing global security
risk-assessment passenger-name-record pnr rules-engine parsing travel advance-passenger-information drools hibernate spring gtas wco customs angular flight un-edifact passenger pnrgov neo4j pentaho-data-integration
Language:Java 109
ghdl / docker
Scripts to build and use docker images including GHDL
actions ci dockerfiles ghdl gtkwave hardware icestorm nextpnr openocd pnr prjtrellis simulation synthesis testbench verilog vhdl vunit yosys
Language:Shell 40
abdelazeem201 / ASIC-Implementation-UART
This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from system clock. If we increase the baud rate, speed of serial data transmission increases. As the dividing factor decrease baud rate increases. in this paper we set the system clock frequency as 50MHz and time to transfer each data bit is 23.75ns with baud rate of 42.1 Mbps (dividing factor is 32). Due to increase in the baud rate the time taken to transfer the data decreases, so it is very useful for faster communication devices. Transmitter and Receiver blocks designed by algorithm state machine method simulated in ModelSim, synthesized in Design Compiler, and extracted in ICC in Nangate 45 nm CMOS cell library.
asic eda fpga pnr rtl soc synthesis uart verilog vhdl
Language:Verilog 9
abdelazeem201 / ICC2_scripts
This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
pnr soc tcl tcl-extension
Language:Tcl 9
porglezomp / minecraft-eda
Electronic design automation for Minecraft
eda logic-synthesis minecraft place-and-route pnr
Language:Python 9
abdelazeem201 / ORCA
Multi-Voltage and Multi-Threshold Low Power Design Techniques for ORCA Processor Based on 32 nm Technology
asic pnr rtl synopsys synopsys-dc synopsys-vcs synthesis upf verilog vhdl synopsys-iccii saed32nm asic-design fpga-soc hdl systemonchip
Language:Verilog 7
basemhesham / Design-and-ASIC-Implementation-of-UART
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
asic dft fm pnr synthesis uart verilog
Language:Verilog 7
Transavia / ShoppingCartExample
Shopping Cart Example
airlines-booking airline flights pnr flights-api shopping-cart
Language:JavaScript 4
crackCodeLogn / PNR_Enquiry_IndianRailways_v2.0
This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand
java java-8 java-swing slf4j indian-railways ticket pnr openfeign apache-commons assertj gson slf4j-api mockito guava lombok
Language:Java 3
mohamedtareq24 / ASIC_implementation_of_PULPino_SoC
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
asic pnr risc-v synopsys-dc synopsys-iccii
Language:Verilog 3
abdelazeem201 / RV32E201X
RV32E201X is a 5-stage pipelined 32-bit RISC-V processor core.
designcomp fpga hdl icc pnr risc-v risc-v32 rtl rv32e201x soc synthesis verilog
Language:Verilog 2
AkshayXPatil / Physical-Layout-Design
Complete design of USART interface with baud rate selection
verilog rtl scripting pnr gdsii gds2 uart vlsi-physical-design
Language:Verilog 2
crackCodeLogn / PNR_Enquiry_IndianRailways
This project caters to the extraction of the status of PNR number (Passenger Name Record) of Indian Railways. PNR number is unique to each and every ticket bought in the railways. With the help of it, we can get the exact details of the ticket in hand
java java-network java-swing indian-railways pnr
Language:Java 2
kholoud0 / ASIC-Implementauion-of-CV32E40S-RISC-V-core-
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
asic implementation pnr synopsys synopsys-dc synopsys-iccii synthesis
Language:SystemVerilog 2
Li-Yueting / aloe-sky130
analog-design eda pnr
Language:Verilog 2
mohamedtareq24 / ASICs_Design_Diploma
RTL to GDSII flow of a low Power configurable multi clock digital system
asics pnr project rtl verilog-hdl
Language:Verilog 2
vipulwairagade / get-pnr-status
Get Coach, Birth Number and Status from your PNR number
pnr pnrstatus birth coach status indian-railways india railway
Language:Python 2
abdelazeem201 / DTMF
Design and Implementation of Goertzel Algorithm for DTMF application on ASIC.
asic dtmf dtmf-tones fpga pnr soc synthesis verilog vhdl
Language:Verilog 1
brijeshyadav2312 / Gaamini-TrainInfo
https://gaamini.netlify.app/
css indian-railways javascript netlify pnr pnrstatus react-app reactjs gaamini
Language:JavaScript 1
praveenpuglia / railly
First Class, Indian Railways Experience
indian railways vue vuetify pnr maps
Language:Vue 1
sangamcse / myPNRStatus
A script in python3 to check PNR status on your terminal
pnr pnrstatus indianrailways indian-railways python-script python-3 python3 python-3-6
Language:Python 1
vsdip / avsdmux2x1_3v3
vsdip kunal123 opensource siliconip ipspecs magic layout characteristics ngspice analog-multiplexer pnr
Language:Shell 1
0marAmr / LP_Multi_Clock_Digital_System
asic-design digital-design formal-verification pnr synthesis
Language:Verilog 0
m1x0n / easy-pnr-api-php
PHP API Client for EasyPNR Decoder
easy-pnr pnr api php
Language:PHP

pnr

efabless / openlane2

US-CBP / GTAS

ghdl / docker

abdelazeem201 / ASIC-Implementation-UART

abdelazeem201 / ICC2_scripts

porglezomp / minecraft-eda

abdelazeem201 / ORCA

basemhesham / Design-and-ASIC-Implementation-of-UART

Transavia / ShoppingCartExample

crackCodeLogn / PNR_Enquiry_IndianRailways_v2.0

mohamedtareq24 / ASIC_implementation_of_PULPino_SoC

abdelazeem201 / RV32E201X

AkshayXPatil / Physical-Layout-Design

crackCodeLogn / PNR_Enquiry_IndianRailways

kholoud0 / ASIC-Implementauion-of-CV32E40S-RISC-V-core-

Li-Yueting / aloe-sky130

mohamedtareq24 / ASICs_Design_Diploma

vipulwairagade / get-pnr-status

abdelazeem201 / DTMF

brijeshyadav2312 / Gaamini-TrainInfo

praveenpuglia / railly

sangamcse / myPNRStatus

vsdip / avsdmux2x1_3v3

0marAmr / LP_Multi_Clock_Digital_System

m1x0n / easy-pnr-api-php