ultraembedded

riscv

RISC-V CPU Core (RV32IM)

biriscv

32-bit Superscalar RISC-V CPU

cores

Various HDL (Verilog) IP Cores

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

FPGAmp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

core_jpeg

High throughput JPEG decoder in Verilog for FPGA

openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

exactstep

Instruction set simulator for RISC-V, MIPS and ARM-v6m

libhelix-mp3

Fixed-point MP3 decoder (RISC-V port)

core_usb_cdc

Basic USB-CDC device core (Verilog)

core_dbg_bridge

UART -> AXI Bridge

core_uriscv

Another tiny RISC-V implementation

core_axi_cache

128KB AXI cache (32-bit in, 256-bit out)

riscv-linux-boot

Trivial RISC-V Linux binary bootloader

core_spiflash

SPI-Flash XIP Interface (Verilog)

core_usb_bridge

USB -> AXI Debug Bridge

core_jpeg_decoder

HW JPEG decoder wrapper with AXI-4 DMA

core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

core_enet

Ethernet MAC 10/100 Mbps

core_mmc

MMC (and derivative standards) host controller

librtos

Very basic real time operating system for embedded systems...

core_mpx

MPX is a open-source CPU which can execute code compiled for MIPS-I ISA

legacy_jpeg_decoder

ecpix5-test

Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board

libsigrok

Read-only mirror of the official repo at git://sigrok.org/libsigrok. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

orangecrab

Test projects for the OrangeCrab ECP5 FPGA board

rp2040_blinky

Simple blinky example for the RP2040 that does not require cmake

openFPGALoader

Universal utility for programming FPGA

ps1-tests

Collection of PlayStation 1 tests for emulator development

.github