ultraembedded

ultraembedded

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Location:UK

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ultraembedded's repositories

riscv

RISC-V CPU Core (RV32IM)

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biriscv

32-bit Superscalar RISC-V CPU

Language:VerilogLicense:Apache-2.0Stargazers:752Issues:26Issues:24

cores

Various HDL (Verilog) IP Cores

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

FPGAmp

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

Language:CLicense:Apache-2.0Stargazers:253Issues:19Issues:0

core_jpeg

High throughput JPEG decoder in Verilog for FPGA

Language:VerilogLicense:Apache-2.0Stargazers:177Issues:10Issues:6

openlogicbit

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

Language:VerilogLicense:Apache-2.0Stargazers:93Issues:8Issues:2

exactstep

Instruction set simulator for RISC-V, MIPS and ARM-v6m

Language:C++License:BSD-3-ClauseStargazers:80Issues:6Issues:1

libhelix-mp3

Fixed-point MP3 decoder (RISC-V port)

Language:CLicense:NOASSERTIONStargazers:72Issues:4Issues:1

core_usb_cdc

Basic USB-CDC device core (Verilog)

Language:VerilogLicense:LGPL-2.1Stargazers:63Issues:5Issues:4

core_uriscv

Another tiny RISC-V implementation

Language:VerilogLicense:Apache-2.0Stargazers:50Issues:5Issues:2

core_dbg_bridge

UART -> AXI Bridge

Language:VerilogLicense:LGPL-2.1Stargazers:44Issues:5Issues:0

riscv-linux-boot

Trivial RISC-V Linux binary bootloader

Language:CLicense:MITStargazers:38Issues:6Issues:1

core_spiflash

SPI-Flash XIP Interface (Verilog)

Language:VerilogLicense:LGPL-2.1Stargazers:34Issues:5Issues:0

core_usb_bridge

USB -> AXI Debug Bridge

Language:VerilogLicense:LGPL-2.1Stargazers:32Issues:8Issues:0

core_jpeg_decoder

HW JPEG decoder wrapper with AXI-4 DMA

Language:VerilogLicense:Apache-2.0Stargazers:26Issues:3Issues:0

core_axi_cache

128KB AXI cache (32-bit in, 256-bit out)

Language:VerilogLicense:BSD-3-ClauseStargazers:25Issues:4Issues:0

core_ftdi_bridge

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

Language:VerilogLicense:GPL-2.0Stargazers:22Issues:4Issues:1

core_enet

Ethernet MAC 10/100 Mbps

Language:VerilogLicense:Apache-2.0Stargazers:21Issues:8Issues:0

core_mmc

MMC (and derivative standards) host controller

Language:VerilogLicense:Apache-2.0Stargazers:21Issues:4Issues:1

librtos

Very basic real time operating system for embedded systems...

Language:CLicense:Apache-2.0Stargazers:14Issues:4Issues:0

core_mpx

MPX is a open-source CPU which can execute code compiled for MIPS-I ISA

Language:VerilogLicense:Apache-2.0Stargazers:9Issues:4Issues:0
Language:VerilogLicense:MITStargazers:8Issues:2Issues:0

libsigrok

Read-only mirror of the official repo at git://sigrok.org/libsigrok. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

Language:CLicense:GPL-3.0Stargazers:7Issues:3Issues:0

ecpix5-test

Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board

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orangecrab

Test projects for the OrangeCrab ECP5 FPGA board

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rp2040_blinky

Simple blinky example for the RP2040 that does not require cmake

Language:C++License:BSD-3-ClauseStargazers:3Issues:3Issues:0

openFPGALoader

Universal utility for programming FPGA

Language:C++License:Apache-2.0Stargazers:2Issues:2Issues:0

ps1-tests

Collection of PlayStation 1 tests for emulator development

Language:C++License:MITStargazers:2Issues:2Issues:0
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