artix-7

There are 5 repositories under artix-7 topic.

ultraembedded / biriscv
32-bit Superscalar RISC-V CPU
risc-v rv32i rv32im superscalar cpu fpga verilog pipelined-processors verilator coremark asic branch-prediction in-order linux riscv-linux xilinx artix-7
Language:Verilog 1119
ultraembedded / FPGAmp
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
artix-7 fpga fpga-media-player hd-video hdmi ir-codes jpeg-decoder mjpeg motion-jpeg risc-v rtos sd-card vga
Language:C 285
ultraembedded / usb2sniffer
USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)
usb-scanning usb-debugging usb usb2 fpga xilinx-vivado rtl verilog usb-analyzer usb-sniffer artix-7 lambdaconcept-usb2sniffer-hardware wireshark
Language:Verilog 58
vankxr / icyradio
Over-engineered SDR development board
ad9361 ad9363 artix-7 broadcast-fm-demodulator cm4 fpga hardware hdl ice40 ice40hx8k mmwave mmwave-5g-networks power-delivery qo-100 qo100 rpi-cm4 sdr software-defined-radio ssb-demodulator usb-pd
Language:VHDL 45
Mario-Hero / Async-Karin
Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.
artix-7 async async-circuit async-karin asynchronous asynchronous-framework cyclone-iv fpga verilog
Language:Verilog 30
Handwritten-Digit-Recognition-Painter
j3soon / Handwritten-Digit-Recognition-Painter
A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.
verilog basys3 artix-7 painter digit-recognition embedded embedded-systems fpga handwritten-digit-recognition artificial-intelligence deep-learning machine-learning neural-network
Language:VHDL 24
briansune / FPGA-Camera-MIPI-DVP-Verilog
FPGA Camera Parallel & MIPI Verilog
fpga kintex7 mipi ov13850 ov4689 verilog xilinx imx291 artix-7 dvp ov2640 ov5640 ov9655
23
HDU_CO_Guide
liolok / HDU_CO_Guide
HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南
vivado artix-7 computer-organization course-design verilog
Language:Verilog 14
f4pga-xc-fasm2bels
chipsalliance / f4pga-xc-fasm2bels
Library to convert a FASM file into BELs importable into Vivado.
fasm vivado tcl verilog bitstream symbiflow artix-7
Language:Verilog 13
briansune / Artix-7-PCIE-Riffa
artix-7 fpga hdl pcie verilog xilinx riffa
Language:Verilog 11
7enTropy7 / Artix_7
My experiments with Nexys4 DDR Artix-7 FPGA Board
artix-7 fpga-programming nexys4ddr verilog verilog-project
Language:Verilog 8
raleighlittles / Applied_Digital_Logic_Exercises_Using_FPGAs
Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.
fpga microblaze-mcs basys3 artix-7 applied-digital-logic-exercises vivado verilog hdl
Language:Verilog 8
Xilinx-Artix-7-PCIe-Project
Chrisdeleon91 / Xilinx-Artix-7-PCIe-Project
Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.
artix-7 pcie-interface vhdl vivado xilinx
Language:VHDL 7
whutddk / verilogRisc
基于蜂鸟E203的魔改
risc-v e203 artix-7
Language:Verilog 7
SnrNotHere16 / FPGADivisionFloatingPoint
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
fpga xilinx xilinx-vivado floating-ip floating-point artix-7 microblaze zynq-7000 zynq sdk c verilog nexys4ddr floating-point-conversion division hdl
Language:VHDL 6
cajt / cmod-a7-35t_leon3
GRLIB GPL support for Digilent CMOD A7 35T board
fpga fpga-soc sparc vhdl leon3 digilent cmod artix-7 grlib
Language:VHDL 5
FallingLights / Audio-Processing-Artix-7
Realtime Audio Processing on Artix-7 FPGA written in VHDL
artix-7 artix7 audio-processing fpga vhdl
Language:VHDL 5
hglee / AlchitryAuFpgaExample
Alchitry Au FPGA Board Example Project
alchitry alchitry-au artix-7 ddr example-project fifo fpga ft600 microblaze-mcs systemverilog uart
Language:SystemVerilog 5
Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg
Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..
7-segment artix-7 basys3 basys3-fpga basys3-fpga-board fibonacci-numbers fibonacci-sequence microprocessor risc-v single-cycle-processor verilog vivado vivado-hls
Language:Tcl 5
whutddk / MK64F-platform
A PCB platform based on the architecture of Arm + FPGA
pcb arm-fpga artix-7 mk64 xc7a35t cortex-m4 xilinx nxp freescale
Language:HTML 5
Yazmau / Verilog-Game-Tetris
A tetris-game on screen using verilog.
hardware verilog basys3-fpga artix-7 tetris-game
Language:Verilog 5
34-Engineering / Virtex-HDL
This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.
systemverilog vivado artix-7 fpga
Language:SystemVerilog 4
tuhalf / SOMvhdl
A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.
som self-organizing-map vhdl fpga data-science arty artix-7 data-mining kohonen-map
Language:VHDL 4
ADolbyB / vhdl-fpga-nexys-a7
A collection of code from CDA 4240C: Design of Digital System and Lab
artix-7 fpga hardware-description-language hdl nexys-a7 verilog vhdl xilinx-vivado
Language:VHDL 3
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 3
briansune / Artix-7-Parallel-OV5640
Artix 7 Parallel OV5640
artix-7 camera ddr3 fpga hdmi ov5640 xga xilinx
3
briansune / FPGA-LCD-MIPI-or-DPI
FPGA LCD MIPI or DPI
anlogic artix-7 cyclone-iv eg4 fpga gc9702p gc9c01 hdl hx8399c jd9365da-h3 jd9522z kintex7 nt35516 spartan6 st7701s st77997 verilog vivado xilinx zynqmp
Language:HTML 3
qubeck78 / tangerineA7_100
RISC-V based SOC for Qmtech Artix7-100 Wukong board with 720p VGA, DDR3 and cache controller
artix-7 ddr3 hdmi vhdl vivado
Language:VHDL 3
Sped0n / ada
An Artix 7 based dual channel oscilloscope.
artix-7 ft232h oscilloscope verilog xc7a35t
Language:VHDL 3
aryan-programmer / axi_stream_array_sum_microblaze
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
artix artix-7 axi axi-lite axi-stream basys3 embedded fpga hls vitis vitis-hls vivado vivado-ip-integrator vivado-vitis xilinx xilinx-fpga xilinx-hls xilinx-vitis xilinx-vivado microblaze
Language:C 2
briansune / Artix-7-Parallel-OV2640
Artix-7-Parallel-OV2640
artix-7 camera ddr3 fpga hdmi ov2640 svga xilinx
2
nikhil-garg / OLED_driver_artix7
OLED driver for artix 7(Nexys 4) FPGA board.
oled fpga artix-7 xilinx-vivado xilinx-sdk ssd1306 driver
Language:C 2
tmahlburg / picosoc-basys3
Wrapper module for the PicoSoC to support the Digilent Basys 3
verilog risc-v picorv32 picosoc xilinx artix artix-7 vivado basys3 digilent
Language:Verilog 2
whutddk / YJ432-PL-PS
ARM+FPGA borad demo
arm-fpga artix-7 cortex-m4 flexbus hw-sw-co-design
Language:C 2
briansune / Artix-7-MIPI-DSI-5-inch-LCD
Artix-7-MIPI-DSI-5-inch-LCD
artix-7 fpga hdl ili9881c lcd-display mipi-dsi tft-display verilog xilinx
1
briansune / FPGA-TFT-MIPI-or-DPI
FPGA-TFT-MIPI-or-DPI
1080p anlogic artix-7 cyclone-iv eg4 fpga gc9c01 hdl hx8399c kintex7 lcd-display mipi-dsi nt35516 spartan6 tft-display verilog xilinx zynqmp
Language:HTML 1

artix-7

ultraembedded / biriscv

ultraembedded / FPGAmp

ultraembedded / usb2sniffer

vankxr / icyradio

Mario-Hero / Async-Karin

j3soon / Handwritten-Digit-Recognition-Painter

briansune / FPGA-Camera-MIPI-DVP-Verilog

liolok / HDU_CO_Guide

chipsalliance / f4pga-xc-fasm2bels

briansune / Artix-7-PCIE-Riffa

7enTropy7 / Artix_7

raleighlittles / Applied_Digital_Logic_Exercises_Using_FPGAs

Chrisdeleon91 / Xilinx-Artix-7-PCIe-Project

whutddk / verilogRisc

SnrNotHere16 / FPGADivisionFloatingPoint

cajt / cmod-a7-35t_leon3

FallingLights / Audio-Processing-Artix-7

hglee / AlchitryAuFpgaExample

Prajjv / RISC-V-Microprocessor-verilog-code-implementation-Artix-7-tested-with-Fibonacci-series-on-7seg

whutddk / MK64F-platform

Yazmau / Verilog-Game-Tetris

34-Engineering / Virtex-HDL

tuhalf / SOMvhdl

ADolbyB / vhdl-fpga-nexys-a7

aryan-programmer / axi_gen_and_sum_primes_fpga

briansune / Artix-7-Parallel-OV5640

briansune / FPGA-LCD-MIPI-or-DPI

qubeck78 / tangerineA7_100

Sped0n / ada

aryan-programmer / axi_stream_array_sum_microblaze

briansune / Artix-7-Parallel-OV2640

nikhil-garg / OLED_driver_artix7

tmahlburg / picosoc-basys3

whutddk / YJ432-PL-PS

briansune / Artix-7-MIPI-DSI-5-inch-LCD

briansune / FPGA-TFT-MIPI-or-DPI