altera

There are 8 repositories under altera topic.

pConst / basic_verilog
Must-have verilog systemverilog modules
fpga delay debounce encoder xilinx altera verilog fifo tcl spi-master synchronizer pwm uart uart-protocol uart-verilog uart-tx uart-receiver uart-controller spi-interface hls
Language:Verilog 1657
hdl-util / hdmi
Send video/audio over HDMI on an FPGA
altera audio dvi fpga hdlmake hdmi intel quartus systemverilog video vivado xilinx
Language:SystemVerilog 1094
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 645
VLSI-EDA / PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 551
f32c / f32c
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
fpga altera lattice xilinx riscv mips arduino
Language:C 404
OpenFPGAduino / OpenFPGAduino
All open source file and project for OpenFPGAduino project
altera arduino arm blockly c cpp fpga grove-shield hardware iiot iot javascript nodejs opensource verilog
Language:Makefile 161
drandyhaas / Haasoscope
Docs, design, firmware, and software for the Haasoscope
altera data-acquisition eagle fpga open-hardware open-source oscilloscope python verilog
Language:Verilog 114
hdl-modules
hdl-modules / hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
altera amd asic axi axi-lite cdc clock-domain-crossing eda efinix fpga hardware intel ip microsemi rtl vhdl vivado xilinx asynchronous-fifo fifo
Language:VHDL 108
PyFPGA / pyfpga
A Python package to use FPGA development tools programmatically.
fpga python tcl xilinx intel microchip lattice ghdl ise libero quartus vivado yosys nextpnr icestorm trellis altera microsemi actel amd
Language:Python 90
thinkoco / c5soc_opencl
DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
opencl vga usb-cameras sobel fpga altera intelfpga de1-soc de10-nano mandelbrot
Language:Verilog 90
awesome-fpga-boards
iDoka / awesome-fpga-boards
:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
awesome awesome-list fpga altera lattice xilinx zynq intel pci-e qsfp ethernet jtag bmc microsoft colorlight ecp5 antminer chubby75
88
hftrx
ua1arn / hftrx
Embedded firmware for ham radio transceivers
stm32 bare-metal cortex-a baremetal cortex-a7 stm32mp1 sdr ham-radio hamradio sdr-radio altera zynq cortex-a9 renesas rza1 ssb allwinner ehci t113-s3
Language:C 81
hukenovs / intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
fft dsp fast-fourier-transform fast-convolutions fpga digital-signal-processing vhdl verilog vivado xilinx altera radix-2 cooley-tukey-fft integer-arithmetic route-optimization
Language:VHDL 77
halfmanhalftaco / fpga-docker
Tools for running FPGA vendor toolchains with Docker
fpga verilog vhdl quartus altera xilinx lattice
Language:Makefile 73
BrianHGinc / BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
ddr3 verilog systemverilog altera intel lattice xilinx testbenches fpga hdl
Language:SystemVerilog 70
mithro / ixo-usb-jtag
usb-jtag - Altera USB Blaster Emulation with a FX2
usb-devices cypress-fx2 jtag altera xilinx fpga ezusb digilent-atlys digilent opsis numato-opsis numato openocd urjtag
Language:C++ 69
suoto / vim-hdl
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
vim-plugins vhdl syntastic altera modelsim xilinx verilog systemverilog productivity syntax-checker
Language:Python 60
hukenovs / fp23fftk
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
fft dsp vhdl verilog xilinx altera fpga digital-signal-processing matlab octave fast-fourier-transform radix-2 cooley-tukey-fft chirp frequency-analysis floating-point ieee754 fast-convolutions convolution convolution-filter
Language:VHDL 55
MJoergen / HyperRAM
Portable HyperRAM controller
hyperram xilinx vivado artix fpga vhdl avalon intel altera lattice quartus modelsim questasim questa
Language:VHDL 48
dilshan / max2-audio-dac
24-bit Stereo Audio DAC for Raspberry Pi
epm240t100c5n cpld altera r-2r dac raspberry-pi i2s-audio audio
Language:Verilog 45
panda5mt / KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
risc-v rv32i fpga chisel3 chisel intel altera avalon-mm riscv
Language:Scala 44
MohammedRashad / FPGA-Speech-Recognition
Expiremental Speech Recognition System using VHDL & MATLAB.
altera audio-processing digital-signal-processing distance domain-signals euclidean-distances fpga hamming-distance matlab pattern-recognition signal speech-recognition speech-recognition-engine uart vhdl
Language:VHDL 43
HPS2FPGAmapping
robseb / HPS2FPGAmapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
altera altera-fpga bootloader can-bus embedded-linux fpga fpga-configuration fpga-fabric fpga-soc hps intel intel-fpga linux mapping-hps-peripherals python-script quartus-prime rsyocto soc-fpga
Language:Verilog 35
thinkoco / de10-nano-riscv
A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
risc-v riscv altera intelfpga de10-nano
Language:Verilog 34
delhatch / Spectrum
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
verilog altera fpga de2-115 rtaudio audio-analysis spectrum-analyzer fft vga vga-frame-buffer
Language:VHDL 28
VladisM / MARK_II
Simple SoC in VHDL with full toolchain and custom board.
vhdl cpu fpga mark-ii soc altera assembler vbcc compiler toolchain intel max10
Language:VHDL 28
leonow32 / verilog-fpga
Many peripherals in Verilog ready to use
altera cpld fpga lattice machxo machxo2 systemverilog verilog xilinx
Language:Verilog 27
sevvalmehder / 32-bit-MIPS-Processor
A 32-bit MIPS processor used Altera Quartus II with Verilog.
mips register opcodes datapath processor altera quartus
Language:Verilog 25
thotypous / alterajtaguart
Altera JTAG UART wrapper for Bluespec
altera bluespec hardware-libraries jtag uart usb-serial-adapters
Language:C 24
HengRuiZ / from-key-array-to-the-LED-lattice
fpga vhdl altera
Language:VHDL 22
b-dmitry1 / V188
FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)
assembler retrocomputing verilog altera fpga emulator
Language:Verilog 21
meta-intelfpga
robseb / meta-intelfpga
Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
altera arria-v arria10 bsp-layer cyclone-v development-tools fpga-configuration fpga-fabric intel-fpga intel-soc-fpgas linux-distribution rsyocto soc-fpga soc-fpga-linux yocto-layer yocto-meta
Language:BitBake 21
Wissance / QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-hdl spi axi spi-ip-core spi-pld spi-fpga spi-interface verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi fpga xilinx-fpga xilinx-vivado altera verilog-snippets verilog-hdl verilog-components
Language:Verilog 20
iDoka / mastering-fpgasic-book
:book: Mastering FPGASIC Book
fpga asic vlsi book verilog vhdl xilinx altera intel synopsys cadence hdl hardware gateware fpgasic engineering diy
18
orangeneko / redphone-pcb
Simple handmade open source mobile phone
stm32 cyclone-iv sim800 mobile-phone altera
18
tomverbeure / intel_jtag_uart
A Python module to interact with an Intel JTAG UART
intel jtag uart fpga python altera jtag-atlantic
Language:Python 18