altera

There are 8 repositories under altera topic.

pConst / basic_verilog
Must-have verilog systemverilog modules
altera debounce delay encoder fifo fpga hls pwm spi-interface spi-master synchronizer tcl uart uart-controller uart-protocol uart-receiver uart-tx uart-verilog verilog xilinx
Language:Verilog 1679
hdl-util / hdmi
Send video/audio over HDMI on an FPGA
hdmi fpga dvi audio video systemverilog hdlmake quartus altera xilinx intel vivado
Language:SystemVerilog 1107
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 650
VLSI-EDA / PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
vhdl poc-library python simulation synthesis verification vlsi testbenches hardware-modules fpga hardware-libraries hardware-designs asic altera xilinx lattice osvvm uvvm vunit regression-testing
Language:VHDL 554
f32c / f32c
A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
altera arduino fpga lattice mips riscv xilinx
Language:C 406
OpenFPGAduino / OpenFPGAduino
All open source file and project for OpenFPGAduino project
javascript nodejs fpga opensource blockly iot arduino grove-shield hardware verilog c cpp altera arm iiot
Language:Makefile 161
hdl-modules
hdl-modules / hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
altera amd asic asynchronous-fifo axi axi-lite cdc clock-domain-crossing eda efinix fifo fpga hardware intel ip microsemi rtl vhdl vivado xilinx
Language:VHDL 118
drandyhaas / Haasoscope
Docs, design, firmware, and software for the Haasoscope
open-hardware open-source data-acquisition oscilloscope python eagle altera fpga verilog
Language:Verilog 116
PyFPGA / pyfpga
A Python package to use FPGA development tools programmatically.
fpga python tcl xilinx intel microchip lattice ghdl ise libero quartus vivado yosys nextpnr icestorm trellis altera microsemi actel amd
Language:Python 94
thinkoco / c5soc_opencl
DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.
altera de1-soc de10-nano fpga intelfpga mandelbrot opencl sobel usb-cameras vga
Language:Verilog 90
awesome-fpga-boards
iDoka / awesome-fpga-boards
:atm: Second life for FPGA boards which can be repurposed to DYI/Hobby projects ...............................................................................................
awesome awesome-list fpga altera lattice xilinx zynq intel pci-e qsfp ethernet jtag bmc microsoft colorlight ecp5 antminer chubby75
88
hftrx
ua1arn / hftrx
Embedded firmware for ham radio transceivers
stm32 bare-metal cortex-a baremetal cortex-a7 stm32mp1 sdr ham-radio hamradio sdr-radio altera zynq cortex-a9 renesas rza1 ssb allwinner ehci t113-s3
Language:C 83
hukenovs / intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
altera cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft fpga integer-arithmetic radix-2 route-optimization verilog vhdl vivado xilinx
Language:VHDL 79
halfmanhalftaco / fpga-docker
Tools for running FPGA vendor toolchains with Docker
fpga verilog vhdl quartus altera xilinx lattice
Language:Makefile 73
BrianHGinc / BrianHG-DDR3-Controller
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
altera ddr3 fpga hdl intel lattice systemverilog testbenches verilog xilinx
Language:SystemVerilog 72
mithro / ixo-usb-jtag
usb-jtag - Altera USB Blaster Emulation with a FX2
usb-devices cypress-fx2 jtag altera xilinx fpga ezusb digilent-atlys digilent opsis numato-opsis numato openocd urjtag
Language:C++ 69
suoto / vim-hdl
Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)
altera modelsim productivity syntastic syntax-checker systemverilog verilog vhdl vim-plugins xilinx
Language:Python 60
hukenovs / fp23fftk
Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).
altera chirp convolution convolution-filter cooley-tukey-fft digital-signal-processing dsp fast-convolutions fast-fourier-transform fft floating-point fpga frequency-analysis ieee754 matlab octave radix-2 verilog vhdl xilinx
Language:VHDL 56
MJoergen / HyperRAM
Portable HyperRAM controller
altera artix avalon fpga hyperram intel lattice modelsim quartus questa questasim vhdl vivado xilinx
Language:VHDL 49
dilshan / max2-audio-dac
24-bit Stereo Audio DAC for Raspberry Pi
epm240t100c5n cpld altera r-2r dac raspberry-pi i2s-audio audio
Language:Verilog 46
MohammedRashad / FPGA-Speech-Recognition
Expiremental Speech Recognition System using VHDL & MATLAB.
altera audio-processing digital-signal-processing distance domain-signals euclidean-distances fpga hamming-distance matlab pattern-recognition signal speech-recognition speech-recognition-engine uart vhdl
Language:VHDL 44
panda5mt / KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
altera avalon-mm chisel chisel3 fpga intel risc-v riscv rv32i
Language:Scala 44
HPS2FPGAmapping
robseb / HPS2FPGAmapping
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
fpga fpga-soc intel-fpga altera altera-fpga embedded-linux can-bus fpga-fabric quartus-prime mapping-hps-peripherals bootloader soc-fpga hps fpga-configuration python-script linux intel rsyocto
Language:Verilog 36
thinkoco / de10-nano-riscv
A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
risc-v riscv altera intelfpga de10-nano
Language:Verilog 34
delhatch / Spectrum
Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.
altera audio-analysis de2-115 fft fpga rtaudio spectrum-analyzer verilog vga vga-frame-buffer
Language:VHDL 29
VladisM / MARK_II
Simple SoC in VHDL with full toolchain and custom board.
altera assembler compiler cpu fpga intel mark-ii max10 soc toolchain vbcc vhdl
Language:VHDL 28
leonow32 / verilog-fpga
Many peripherals in Verilog ready to use
altera cpld fpga lattice machxo machxo2 systemverilog verilog xilinx
Language:Verilog 27
sevvalmehder / 32-bit-MIPS-Processor
A 32-bit MIPS processor used Altera Quartus II with Verilog.
altera datapath mips opcodes processor quartus register
Language:Verilog 26
thotypous / alterajtaguart
Altera JTAG UART wrapper for Bluespec
jtag uart bluespec altera usb-serial-adapters hardware-libraries
Language:C 24
HengRuiZ / from-key-array-to-the-LED-lattice
altera fpga vhdl
Language:VHDL 22
b-dmitry1 / V188
FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)
altera assembler emulator fpga retrocomputing verilog
Language:Verilog 21
meta-intelfpga
robseb / meta-intelfpga
Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
altera arria-v arria10 bsp-layer cyclone-v development-tools fpga-configuration fpga-fabric intel-fpga intel-soc-fpgas linux-distribution rsyocto soc-fpga soc-fpga-linux yocto-layer yocto-meta
Language:BitBake 21
Wissance / QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-hdl spi axi spi-ip-core spi-pld spi-fpga spi-interface verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi fpga xilinx-fpga xilinx-vivado altera verilog-snippets verilog-hdl verilog-components
Language:Verilog 20
orangeneko / redphone-pcb
Simple handmade open source mobile phone
stm32 cyclone-iv sim800 mobile-phone altera
19
iDoka / mastering-fpgasic-book
:book: Mastering FPGASIC Book
altera asic book cadence diy engineering fpga fpgasic gateware hardware hdl intel synopsys verilog vhdl vlsi xilinx
18
tomverbeure / intel_jtag_uart
A Python module to interact with an Intel JTAG UART
altera fpga intel jtag jtag-atlantic python uart
Language:Python 18