uvm-register-model

There are 5 repositories under uvm-register-model topic.

rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 280
SystemRDL / PeakRDL
Control and status register code generator toolchain
asic fpga eda registers register-descriptions systemrdl-compiler hardware-description-language command-line-tool amba apb axi csr systemverilog uvm uvm-register-model verilog
Language:Python 74
SystemRDL / PeakRDL-uvm
Generate UVM register model from compiled SystemRDL input
uvm-register-model uvm-ral-model asic fpga uvm eda registers
Language:Python 45
rggen / rggen-sample-testbench
systemverilog uvm uvm-ral-model uvm-register-model verilog vhdl
Language:VHDL 14
rggen / rggen-sv-ral
UVM RAL class package for RgGen
ral systemverilog uvm uvm-ral-model uvm-register-model
Language:SystemVerilog 6