gdsii
There are 10 repositories under gdsii topic.
The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
Language:Verilog 1513- gdsfactory
gdsfactory / gdsfactory
python library to design chips (Photonics, Analog, Quantum, MEMs, ...), objects for 3D printing or PCBs.
Language:Python 499 - Language:Python 348
heitzmann / gdstk
Gdstk (GDSII Tool Kit) is a C++/Python library for creation and manipulation of GDSII and OASIS files.
Language:C++ 335OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Language:Verilog 315trilomix / GDS3D
GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation of the layout, where the user has full, real time control over the camera position and angle, much like in a 3D video game. An other repo (https://github.com/skuep/GDS3D) as the same source and add few improvement like compression with server/client process. This release add two major feature with are assembly and export 3D model for GMSH. Assembly: this mean it’s possible to merge multi GDS (with different technologies) I also try to improve net highlight.
Language:C++ 195- Language:Python 193
efabless / openlane2
The next generation of OpenLane, rewritten from scratch with a modular architecture
Language:Python 191iqm-finland / KQCircuits
KLayout Python library for integrated quantum circuit design.
Language:Python 131purdue-onchip / gds2Para
GDSII File Parsing, IC Layout Analysis, and Parameter Extraction
Language:C++ 110HelgeGehring / gdshelpers
GDSHelpers is an open-source package for automatized pattern generation for nano-structuring.
Language:Python 109Hideousmon / SPLayout
Silicon Photonics Design Tools.
Language:Python 48- Language:Python 36
gdsfactory plugins
Language:Python 35- Language:C++ 28
- Language:C++ 21
PainterQubits / Devices.jl
Julia package for CAD of superconducting devices operating at microwave frequencies.
Language:Julia 21- Language:TypeScript 17
- Language:Python 17
ahryciw / Raith_GDSII
MATLAB tools for Raith electron-beam lithography (EBL) and focused ion beam (FIB) systems — Outils MATLAB pour les systèmes Raith de lithographie par faisceau d'électrons et de faisceau d'ions focalisés
Language:MATLAB 13- gds2vec
hzeller / gds2vec
A simple program to convert gdsII files to vector output formats. Currently used to create laser-cut models of standard cells.
Language:C++ 12 - Language:Python 11
- Language:Python 10
refob / load_lefdef_tutorial
This is a brief tutorial that shows how to load GDS or LEF/DEF data into KLayout. The first step is to convert a Cadence techology into Klayout property file format. Then we use this configuration to display a small cmos design using either gds or LEF/DEF input format.
Language:HCL 6EGelphman97 / Optical-Filter-Synthesis
This repository has code for a Python program that synthesizes an optical filter
Language:Python 5AkshayXPatil / MSDAP
Complete design of a Mini Stereo Digital Audio Processor
Language:Verilog 3BorisGerretzen / GdsSharp
A C# library for reading, editing, and writing Calma GDSII files.
Language:C# 3- Language:C++ 3
Complete design of USART interface with baud rate selection
Language:Verilog 2- Language:Common Lisp 2
- Language:Python 2
- Language:TypeScript 2
- Language:Verilog 1
tpolakovic / DeviceLib
Python library for quick design of superconducting nanowire devices.
Language:Python 1- gdschamfer
arun-goud / gdschamfer
Python add-on module for gdspy that can perform chamfering operation on GDSII files
Language:Python 0 KAMATHAM19 / RTL-to-GDSII-ASIC-design-of-Counter
The objective is to take a simple counter design from the RTL (Register Transfer Level) stage to the GDSII format using Cadence tools with a 90nm Process Design Kit (PDK).. The tools used in this process include Xcelium for simulation and coverage analysis, Genus for synthesis, Innovus for physical design, and Pegasus/PVS for physical verification.
Language:Tcl 0
