systemc

There are 16 repositories under systemc topic.

verilator
verilator / verilator
Verilator open-source SystemVerilog simulator and lint system
compilers cpp rtl system-verilog systemc verilator verilog verilog-simulator
Language:C++ 3160
sergeykhbr / riscv_vhdl
Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
cpu debugger qt riscv simulator soc systemc vhdl
Language:C++ 674
accellera-official / systemc
SystemC Reference Implementation
cpp systemc tlm
Language:C++ 617
mariusmm / RISC-V-TLM
RISC-V SystemC-TLM simulator
risc-v riscv systemc tlm2
Language:C 329
intel / systemc-compiler
This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
systemc hls hardware-designs llvm clang
Language:C++ 292
davidepatti / noxim
Network on Chip Simulator
network-analysis noc noxim simulation systemc university
Language:C++ 289
tymonx / logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
verilog systemverilog hdl systemc uvm cpp cmake modelsim verilator verification rtl unit-tests quartus fpga asic testing-rtl xilinx vivado
Language:SystemVerilog 283
Xilinx / libsystemctlm-soc
SystemC/TLM-2.0 Co-simulation framework
co-simulation qemu systemc tlm2
Language:Verilog 259
Nic30 / hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
verilog vhdl fpga hls simulator hcl uvm systemverilog codegenerator codegen compiler rtl systemc
Language:Python 218
agra-uni-bremen / riscv-vp
RISC-V Virtual Prototype
cpu risc-v riscv simulator soc system-c systemc systemc-tlm tlm tlm2 virtual-prototype vp
Language:C++ 179
machineware-gmbh / vcml
A modeling library with virtual components for SystemC and TLM simulators
systemc tlm-models
Language:C++ 172
ultraembedded / riscv_soc
Basic RISC-V Test SoC
risc-v system-on-chip verilog systemc fpga-soc fpga-soc-linux linux riscv-linux
Language:Verilog 159
Xilinx / systemctlm-cosim-demo
QEMU libsystemctlm-soc co-simulation demos.
co-simulation qemu systemc tlm2
Language:C++ 155
Minres / SystemC-Components
A SystemC productivity library: https://minres.github.io/SystemC-Components/
systemc c-plus-plus c-plusplus
Language:C++ 124
nelsoncsc / ISP_UVM
A Framework for Design and Verification of Image Processing Applications using UVM
functional-verification hardware-designs image-processing opencv systemc systemverilog-hdl uvm
Language:SystemVerilog 110
AleksandarKostovic / SystemC-tutorial
Brief SystemC getting started tutorial
cpp cplusplus systemc
Language:C++ 93
anikau31 / systemc-clang
This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
systemc systemc-clang plugin-hdl verilog synthesis
Language:C++ 88
Xilinx / pcie-model
PCI Express controller model
c co-simulation pcie systemc tlm2
Language:C 68
varunnagpaal / Digital-Hardware-Modelling
Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
vhdl systemverilog vlsi hls rtl systemc digital-hardware hardware-models fpga digital-systems hardware opencl verilog
Language:VHDL 67
Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
An example of using Ramulator as memory model in a cycle-accurate SystemC Design
systemc cycle-accurate accelerator ramulator ddr
Language:C++ 53
agra-uni-bremen / crave
Constrained random stimuli generation for C++ and SystemC
constrained-random systemc
Language:C++ 52
xver / Shunt
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
systemverilog verilog asic dpi open-source opensource system socket tcp ip systemverilog-dpi tcp-socket systemverilog-simulation ip-shunt tlm tlm2 ip-socket communication systemc python
Language:C 49
tymonx / virtio
Virtio implementation in SystemVerilog
verilog systemverilog hdl rtl cmake verilator virtio quartus fpga xilinx vivado model systemc
Language:SystemVerilog 47
mitya1337 / Simple_I2C
Simple implementation of I2C interface written on Verilog and SystemC
verilog systemc i2c
Language:C++ 44
Nic30 / hdlConvertorAst
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
codegen codegenerator fpga python systemc systemverilog verilog vhdl
Language:Python 39
Minres / DBT-RISE-RISCV
An instruction set simulator based on DBT-RISE implementing the RISC-V ISA
dbt iss llvm systemc risc-v
Language:C++ 36
SingularityKChen / SystemC-Training
SystemC training aimed at TLM.
systemc tlm
Language:C++ 34
jessebarreto / NetworkOnChip
Development of a Network on Chip Simulation using SystemC.
systemc cpp cpp11 noc
Language:C++ 33
SoCMake
HEP-SoC / SoCMake
CMake based hardware build system
asic build-automation build-system cmake fpga integrated-circuits system-on-chip systemc systemverilog verilator verilog vhdl vhdl-language
Language:CMake 32
PAT-Noxim
amin-norollah / PAT-Noxim
cycle accurate Network-on-Chip Simulator
pat-noxim simulator noc orion noc-simulator noxim access-noxim hardware-simulator university systemc network-analysis
Language:C 31
Minres / SystemC-Quickstart
A simple C++ CMake project to jump-start development of SystemC models and systems
c-plus-plus c-plusplus systemc
Language:C++ 29
agra-uni-bremen / symex-vp
A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
concolic-execution concolic-testing klee risc-v riscv riscv32 symbolic-execution systemc
Language:C++ 26
timurkelin / simsimd
Development and simulation framework for Application Specific Vector Processor
simd single-instruction-multiple-data asip application-specific architecture vector-processor cycle-accurate data-driven system-simulation systemc model-based dsp digital-signal-processing vector-core network-on-chip heterogeneous-structure heterogeneous-computing system-level-simulation multimode-processing simulation-framework
Language:C++ 16
brilacasck / micro-acc-systemc
simulating connection of micro processor and accelerator on a bus context with systemc language
systemc cpp c micro-processor accelerator micro cpu bus communication datapath architecture hardware software hw-sw-co-design hardware-software co-design alu pc memory controller
Language:C++ 15
Minres / HIFIVE1-VP
A Virtual platform using DBT-RISE-RISCV capable of running unmodified FreeRTOS
dbt iss llvm systemc risc-v virtual-platform
Language:C++ 14
Risto97 / systemc_uvm_verilator
systemc uvm accellera verilator pygears verilog fpga
Language:C++ 13