There are 6 repositories under axi topic.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Network on Chip Implementation written in SytemVerilog
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
OPAE porting to Xilinx FPGA devices.
Xilinx PCIe to MIG DDR4 example designs and custom part data files
An open-source HDL register code generator fast enough to run in real time.
Implementation of the Advanced Encryption Standard in Chisel
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
Hardware and Software Co-design implementations
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
Pothos FPGA computational offload and buffer integration support
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
Userspace I/O library for Xilinx AXI S2MM DMA
This project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"
Basic JTAG / AXI demonstration on Xilinx's FPGA.
Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.
Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)