axi

There are 6 repositories under axi topic.

pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
asic axi axi4 axi4-lite fpga hardware ip network-on-chip rtl systemverilog
Language:SystemVerilog 937
taichi-ishitani / tvip-axi
AMBA AXI VIP
systemverilog uvm amba amba-axi axi axi4 vip
Language:SystemVerilog 302
rggen / rggen
Code generation tool for control and status registers
verilog systemverilog uvm rtl ral csr soc fpga asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda vhdl wishbone-bus
Language:Ruby 280
ZipCPU / sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
sd-card sd-interface fpga verilog-components verilog verilator wishbone wishbone-bus spi-interface axi emmc sdio
Language:Verilog 140
taichi-ishitani / tnoc
Network on Chip Implementation written in SytemVerilog
noc network-on-chip systemverilog amba amba-axi axi axi4 uvm
Language:SystemVerilog 133
lucky-wfw / ARM_AMBA_Design
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
verilog amba arm apb ahb axi
Language:Verilog 96
SystemRDL / PeakRDL
Control and status register code generator toolchain
asic fpga eda registers register-descriptions systemrdl-compiler hardware-description-language command-line-tool amba apb axi csr systemverilog uvm uvm-register-model verilog
Language:Python 74
hdl-modules
hdl-modules / hdl-modules
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
altera amd asic axi axi-lite cdc clock-domain-crossing eda efinix fpga hardware intel ip microsemi rtl vhdl vivado xilinx asynchronous-fifo fifo
Language:VHDL 57
opae-xilinx
RSPwFPGAs / opae-xilinx
OPAE porting to Xilinx FPGA devices.
fpga fpga-accelerator xilinx pcie opae platform-reuse partial-reconfiguration axi
Language:Coq 38
d953i / Custom_Part_Data_Files
Xilinx PCIe to MIG DDR4 example designs and custom part data files
ddr4 ddr mig xilinx vcu1525 bcu1525 sqrl csv tcl vivado axi dimm udimm rdimm sodimm calibration fpga verilog
Language:Tcl 32
pulp-platform / axi_mem_if
Simple single-port AXI memory interface
asic axi fpga systemverilog-hdl
Language:SystemVerilog 32
esynr3z / axi_vip_demo
Xilinx AXI VIP example of use
axi fpga systemverilog xilinx
Language:SystemVerilog 28
hdl-registers
hdl-registers / hdl-registers
An open-source HDL register code generator fast enough to run in real time.
asic axi eda fpga rtl axi-lite register register-interface csr generator html python vhdl c cplusplus
Language:Python 21
hplp / aes_chisel
Implementation of the Advanced Encryption Standard in Chisel
aes advanced-encryption-standard chisel firrtl verilog rocc axi avalon parameterized
Language:Scala 20
Wissance / QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-hdl spi axi spi-ip-core spi-pld spi-fpga spi-interface verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi fpga xilinx-fpga xilinx-vivado altera verilog-snippets verilog-hdl verilog-components
Language:Verilog 18
pulp-platform / axi_node
AXI X-Bar
axi systemverilog asic fpga
Language:SystemVerilog 17
mwrnd / innova2_xcku15p_ddr4_bram_gpio
XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA
axi ddr4 fpga vivado xcku15p xdma mnv303212a pcie innova2 innova-2-flex 4xc7a16683 01pg974 mnv303212a-adlt pcie-xdma
Language:Tcl 12
Yourigh / Rotary-encoder-VHDL-design
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
rotary encoder axi vivado xilinx-vivado xilinx-fpga zybo zynq zynq-7010
Language:VHDL 12
rggen / rggen-sv-rtl
Common SystemVerilog RTL modules for RgGen
systemverilog rtl apb axi4 axi
Language:SystemVerilog 11
bselimoglu / SoC-ZedBoard-Zynq-7000-Labs
Hardware and Software Co-design implementations
fsm zedboard zynq-7000 vivado-ip-integrator arm-cortex-a9 sdk zynq7-ps gpio axi ddr dma bram high-performance-port
9
kuoyaoming93 / sem-ip_pynq
SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2
soft-error xilinx xilinx-vivado xilinx-fpga zynq pynq pynq-hardware-overlay pynq-z1 pynq-z2 python uart axi icap jupyter-notebook sem-ip
Language:Tcl 9
pothosware / PothosFPGA
Pothos FPGA computational offload and buffer integration support
pothos fpga xilinx stream axi pothos-framework
Language:VHDL 9
olagrottvik / bust
Utility for creating and modifying VHDL bus slave modules
axi python3 vhdl
Language:Python 7
plasoc / axiplasma
AXI/MIPS SoC developed in VHDL with FreeRTOS port. Capable of running either preemptively or cooperatively.
mips system-on-chip real-time operating-system vhdl freertos axi amba vivado xilinx c
Language:VHDL 7
vedranMv / axi_spi_master
IP core for a simple SPI master with variable clock frequncy within AXI peripheral. Developed and tested on Zybo evaluation board (Zynq-7000 product family)
vhdl-modules spi axi axi-spi ip-core
Language:VHDL 7
aunics / AHB5
AMBA AHB 5.0 VIP in SystemVerilog based on UVM
system verilog ahb axi uvm
Language:SystemVerilog 6
gednyengs / dma
Open-Source AXI4 DMA Engine in SystemVerilog and Chisel
dma axi4 axi chisel systemverilog stanford-aha stanford
Language:Scala 6
MicroTCA-Tech-Lab / libudmaio
Userspace I/O library for Xilinx AXI S2MM DMA
axi dma fpga pcie soc uio userspace-driver xdma
Language:C++ 6
abdelazeem201 / Arm-Core
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
amba armv4 armv6 armv7 armv9 axi c fpga soc verilog vhdl vhdl-code systemverilog
Language:C 5
tanerguven / StreamIF
This project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"
fpga axis axi zynq
Language:Verilog 5
jchengX / AXI_DRIVER
axi systemverilog uvm
Language:SystemVerilog 4
mrengineer / Zynq7000_simpleDMA_IRQ_vivado_linux_userspace
Complete project in Vivado 2022.1 + userspace app for petalinux. Loopback AXI simple DMA transfer.
axi dma petalinux
Language:VHDL 4
MatthieuMichon / fpga-jtag-axi-demo
Basic JTAG / AXI demonstration on Xilinx's FPGA.
fpga jtag axi systemverilog xilinx vivado tcl
Language:Tcl 3
pulp-platform / axi2per
AXI to Peripheral Interconnect
axi systemverilog-hdl fpga asic
Language:SystemVerilog 3
AranelLindi / AXI_SpaceWire_IP
Standalone IP with ARM-AMBA/AXI capable device. Enables sending and receiving data via SpaceWire protocol. Tested on Xilinx FPGA (ZYNQ).
arm axi soc spacewire xilinx zynq
Language:VHDL 2
aryan-programmer / axi_gen_and_sum_primes_fpga
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
artix artix-7 basys3 fpga vitis vivado xilinx xilinx-fpga axi axi-lite axi-memory-mapped axi-stream embedded hls vitis-hls vivado-ip-integrator vivado-vitis xilinx-hls xilinx-vitis xilinx-vivado
Language:TeX 2

axi

pulp-platform / axi

taichi-ishitani / tvip-axi

rggen / rggen

ZipCPU / sdspi

taichi-ishitani / tnoc

lucky-wfw / ARM_AMBA_Design

SystemRDL / PeakRDL

hdl-modules / hdl-modules

RSPwFPGAs / opae-xilinx

d953i / Custom_Part_Data_Files

pulp-platform / axi_mem_if

esynr3z / axi_vip_demo

hdl-registers / hdl-registers

hplp / aes_chisel

Wissance / QuickSPI

pulp-platform / axi_node

mwrnd / innova2_xcku15p_ddr4_bram_gpio

Yourigh / Rotary-encoder-VHDL-design

rggen / rggen-sv-rtl

bselimoglu / SoC-ZedBoard-Zynq-7000-Labs

kuoyaoming93 / sem-ip_pynq

pothosware / PothosFPGA

olagrottvik / bust

plasoc / axiplasma

vedranMv / axi_spi_master

aunics / AHB5

gednyengs / dma

MicroTCA-Tech-Lab / libudmaio

abdelazeem201 / Arm-Core

tanerguven / StreamIF

jchengX / AXI_DRIVER

mrengineer / Zynq7000_simpleDMA_IRQ_vivado_linux_userspace

MatthieuMichon / fpga-jtag-axi-demo

pulp-platform / axi2per

AranelLindi / AXI_SpaceWire_IP

aryan-programmer / axi_gen_and_sum_primes_fpga