soc-design

There are 1 repository under soc-design topic.

The-OpenROAD-Project / OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
asic 130nm magic netgen yosys openroad skywater openram vlsi system-on-chip soc-design rtl2gds foundry rtl verilog klayout caravel
Language:Python 1620
arm-university / Advanced-System-on-Chip-Design-Education-Kit
Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages
cortex-a9 fpga arm armv7 soc-design arm-cortex-a9 amba cortex-a hardware-designs system-on-chip-design zybo-z7-10
Language:HTML 114
arm-university / Fundamentals-of-System-on-Chip-Design-on-Arm-Cortex-M-Microcontrollers
A textbook on understanding system on chip design
amba arm-cortex-m fpga fpga-soc soc-design system-on-chip-design cmsis cpu-architecture embedded-systems trustzone bus-architecture soc textbook
50
arm-university / Modern-System-on-Chip-Design-on-Arm
A textbook on system on chip design using Arm Cortex-A
soc-design system-on-chip-design fpga-soc soc system-design hardware-designs computer-architecture arm-cortex-a textbook
36
arm-university / System-on-Chip-Design-with-Arm-Cortex-M-Processors
A reference book on System-on-Chip Design
amba cortex-m embedded-systems soc-design software-design system-on-chip-design arm-cortex-m keil-mdk bus-architecture cortex-m-processors reference-book
36
nekosilverfox / ZYNQ
⚙️ 基于 Zynq-7 全可编程 SoC 的设计
fpga sdk soc-design soc-fpga verilog vivado xilinx zynq zynq-7000 zynq-7010 zynq-7020
Language:HTML 36
RISMicroDevices / OpenNCB
Open-source Non-coherent CHI Bridge (CHI SN-F to AXI-4 bridge)
amba amba-axi amba-chi axi axi4 bus chi chisel chisel3 protocol-converter soc soc-design protocol-bridge
Language:Scala 9
williaml33moore / bathtub
BDD Gherkin implementation in native SystemVerilog, based on UVM.
asic asic-design asic-verification bdd bdd-framework bdd-specs design-verification fpga rtl rtl-design soc-design soc-verification systemverilog uvm uvm-verification verilog verilog-hdl
Language:SystemVerilog 8
Vor-Art / DCD_MultiBankMemory
SystemVerilog implementation of a multi-bank memory as part of "[F23] Digital Circuit Design" course
soc-design systemverilog throughput multibank-memory innopolis-university fpga
Language:SystemVerilog 7
iamstan13y / fomalhaut-microservices
microservices-architecture asp-net-core redis mongodb postgresql docker grpc-service web-api dapper solid-principles cqrs-pattern soc-design mediator-pattern fluentvalidation rabbit-mq ocelot-api-gateway aggregator-services bootstrap razor-pages
Language:C# 6
Lawrence-Leung / YogurtNet
Entries for the 2023 5th National College Student Integrated Circuit EDA Elite Challenge. SoC chip physical layout static IR drop prediction project based on methods such as image processing and NLP unsupervised learning.
cnn electronic-design-automation ir-drop machine-learning physical-layout-analysis power-network signoff soc-design u-net u-net-pytorch unsupervised-learning vlsi-physical-design word2vec pix2pix
Language:Python 6
amitops2103 / NASSCOM_VSD_SoC_Physical_Design_Program
Digital VLSI Soc-Physical Design (Picorv32)
physical-layout-analysis soc-design vlsi-physical-design
2
hummingbird-12 / soc-design
Workspace for CSE4178 - Basic SoC Design course (기초SOC설계), Fall 2020, Sogang University
cse4178 hdl magic soc soc-design sogang spice verilog vhdl vivado
Language:Tcl 1
rehanmq / asic-soc-ml-accelerator-verification
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
ai-hardware asic-verification msp432 soc-design system-design systemverilog verilator
Language:Verilog 1
Teimir / Ether-Simple-Proc
Репозиторий пэт проекта 8-и битного процессора
cpu cpu-simulator hdl soc soc-design systemverilog
Language:SystemVerilog 1
hp298 / Verilog-FPGA
ECE2300: Digital Logic and Computer Organization
verilog fpga soc-design
Language:Verilog 0