sky130
There are 3 repositories under sky130 topic.
efabless / caravel
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Language:Verilog 263The next generation of OpenLane, rewritten from scratch with a modular architecture
Language:Python 168Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
Language:Verilog 134- open-source-pdks
google / open-source-pdks
Index of the fully open source process design kits (PDKs) maintained by Google.
ShonTaware / SRAM_SKY130
Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
Language:SourcePawn 51- skywater-pdk-sky130-raw-data
Raw data collected about the SKY130 process technology.
Language:Jupyter Notebook 48 iic-jku / osic-multitool
JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
Language:Shell 48AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
- Language:Makefile 37
Fully-differential asynchronous non-binary 12-bit SAR-ADC in SKY130, free to re-use under Apache-2.0 license
Language:Verilog 34ACMmodel / MOSFET_model
A simple MOSFET model with only 5-DC-parameters for circuit simulation
This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
mattvenn / flipflop_demo
Flip flop setup, hold & metastability explorer tool
Language:Jupyter Notebook 29stineje / sky130RHBDlib
Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
Language:Tcl 28w32agobot / SKY130_SAR-ADC
Fully-differential asynchronous non-binary 12-bit SAR-ADC
Language:Verilog 24- skywater-pdk-libs-sky130_fd_pr
Primitives for SKY130 provided by SkyWater.
ChrisZonghaoLi / sky130_ldo_rl
This repo contains the code that runs RL+GNN to optimize LDOs in SKY130 process.
Language:Jupyter Notebook 21- skywater-pdk-libs-sky130_fd_bd_sram
SRAM build space for SKY130 provided by SkyWater.
- skywater-pdk-libs-sky130_bag3_pr
BAG (BAG AMS Generator) Primitives Library for SKY130
Language:Python 16 - skywater-pdk-libs-sky130_fd_sc_hd
"High density" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 15 aasthadave9 / Advanced-Physical-Design-Using-OpenLANE-Sky130
This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an opensource RTL2GDS flow using OpenLANE and opensource PDK provided by Google/SkyWater130
Instrumenting adders to measure speed
Language:Verilog 12Project 1.1 Simulate a Skywater 130nm standard cell using ngspice
Language:Makefile 11- Language:Verilog 11
- Language:Python 10
chennakeshavadasa / Low-dropout-Voltage-Regulator-LDO-using-SKY130PDK
Design of LDO using open source SKY130PDK
eescottie / opensrc_analog
Providing examples on how to setup and use xschem, ngspice, and gaw, to do analog IC design
Language:Shell 8- skywater-pdk-libs-sky130_fd_io
IO and periphery cells for SKY130 provided by SkyWater.
Language:Verilog 8 michaelk99 / SKY130_CT-DSM
A case study of a continuous-time Delta-Sigma modulator including system-level simulations/design of the CT-DSM, circuit-design of the front-end Gm-cell and a mixed-signal simulation w/ Ngspice.
Language:Jupyter Notebook 7shalan / MS_QSPI_XIP_CACHE
AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP
Language:Verilog 7Template project for the Zero to ASIC course group ASIC application
Language:Verilog 6- Language:Jupyter Notebook 6
Design of miller compensated 2 stage opamp using open source SKY130PDK
- skywater-pdk-libs-sky130_fd_sc_hdll
"High density, low leakage" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 5 - skywater-pdk-libs-sky130_fd_sc_ls
"Low speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 5 - skywater-pdk-libs-sky130_fd_sc_ms
"Medium speed" digital standard cells for SKY130 provided by SkyWater.
Language:Verilog 5
