System Level Design Group @ Columbia University

esp

Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy

hl5

A 32-bit RISC-V Processor Designed with High-Level Synthesis

esp-caches

SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol

zynq-template

Template design and boot image for ZYNQ and ZYNQ Ultrascale+ Development Boards

spikehard

The open-source release of "SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip"

esp-accelerator-templates

ESP Accelerator Templates

axi

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

esp-docker

Repository to create docker image for ESP

ariane

Ariane is a 6-stage RISC-V CPU capable of booting Linux

nvdla-hw

RTL, Cmodel, and testbench for NVDLA

esp-chisel-accelerators

Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

axi_riscv_atomics

AXI Adapter(s) for RISC-V Atomic Operations

linux

riscv-dift

rv_plic

Development Fork (unstable)

sld-lib-jenkins

Shared library for Jenkins

buildroot

Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.

common_cells

Common SystemVerilog components

cryo-ai-models

memgen

Memory Generator for High Level Synthesis of ESP Accelerators

noc-tb

nvdla-sw

NVDLA SW

opensbi

RISC-V Open Source Supervisor Binary Interface

riscv-pk

RISC-V Proxy Kernel

vortex