System Level Design Group @ Columbia University's repositories
esp-caches
SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
zynq-template
Template design and boot image for ZYNQ and ZYNQ Ultrascale+ Development Boards
esp-accelerator-templates
ESP Accelerator Templates
esp-docker
Repository to create docker image for ESP
axi_riscv_atomics
AXI Adapter(s) for RISC-V Atomic Operations
esp-chisel-accelerators
Chisel wrapper and accelerators for Columbia's Embedded Scalable Platform (ESP)
riscv-cores-list
RISC-V Cores, SoC platforms and SoCs
sld-lib-jenkins
Shared library for Jenkins
buildroot
Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
common_cells
Common SystemVerilog components
opensbi
RISC-V Open Source Supervisor Binary Interface
opentitan
OpenTitan: Open source silicon root of trust
riscv-pk
RISC-V Proxy Kernel