Olof Kindgren's repositories
subservient
Small SERV-based SoC primarily for OpenMPW tapeout
wb_intercon
Wishbone interconnect utilities
fusesocotb
Quick'n'dirty FuseSoC+cocotb example
spi_ram_loader
SPI RAM loader
riscv-formal
RISC-V Formal Verification Framework
riscv-opcodes
RISC-V Opcodes
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
Booth_Multipliers
Parameterized Booth Multiplier in Verilog 2001
hossein1387.github.io
Personal Website
000
Language:C++000
minimax
Minimax: a Compressed-First, Microcoded RISC-V CPU
Language:AssemblyBSD-3-Clause000
qspiflash
A set of Wishbone Controlled SPI Flash Controllers
Language:Verilog000
salsa20
Sals20 Stream Cipher core in Verilog
Language:VerilogBSD-2-Clause000
subservient_gfmpw1
https://caravel-user-project.readthedocs.io
Apache-2.0000
Language:VerilogApache-2.0000
Apache-2.0000
usbcorev
A full-speed device-side USB peripheral core written in Verilog.
Language:VerilogNOASSERTION000
verilog-dsp
Verilog digital signal processing components