Olof Kindgren's repositories

serv

SERV - The SErial RISC-V CPU

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fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

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edalize

An abstraction library for interfacing EDA tools

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corescore

CoreScore

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ipyxact

Python-based IP-XACT parser

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subservient

Small SERV-based SoC primarily for OpenMPW tapeout

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wb_intercon

Wishbone interconnect utilities

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fusesocotb

Quick'n'dirty FuseSoC+cocotb example

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spi_ram_loader

SPI RAM loader

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opentitan

OpenTitan: Open source silicon root of trust

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riscv-formal

RISC-V Formal Verification Framework

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zipcpu

A small, light weight, RISC CPU soft core

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openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

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riscv-opcodes

RISC-V Opcodes

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basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

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blabla

Implementation of the BlaBla version of the ChaCha stream cipher

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Booth_Multipliers

Parameterized Booth Multiplier in Verilog 2001

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hossein1387.github.io

Personal Website

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minimax

Minimax: a Compressed-First, Microcoded RISC-V CPU

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prince

The Prince lightweight block cipher in Verilog.

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qspiflash

A set of Wishbone Controlled SPI Flash Controllers

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salsa20

Sals20 Stream Cipher core in Verilog

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subservient_gfmpw1

https://caravel-user-project.readthedocs.io

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usbcorev

A full-speed device-side USB peripheral core written in Verilog.

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verilog-dsp

Verilog digital signal processing components

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