Olof Kindgren's repositories
subservient
Small SERV-based SoC primarily for OpenMPW tapeout
wb_intercon
Wishbone interconnect utilities
fusesocotb
Quick'n'dirty FuseSoC+cocotb example
spi_ram_loader
SPI RAM loader
riscv-formal
RISC-V Formal Verification Framework
Booth_Multipliers
Parameterized Booth Multiplier in Verilog 2001
riscv-opcodes
RISC-V Opcodes
basejump_stl
BaseJump STL: A Standard Template Library for SystemVerilog
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Language:PythonBSD-3-Clause000
hossein1387.github.io
Personal Website
000
salsa20
Sals20 Stream Cipher core in Verilog
Language:VerilogBSD-2-Clause000
subservient_gfmpw1
https://caravel-user-project.readthedocs.io
Apache-2.0000
Language:VerilogApache-2.0000
Apache-2.0000
usbcorev
A full-speed device-side USB peripheral core written in Verilog.
Language:VerilogNOASSERTION000