RgGen

rggen

Code generation tool for control and status registers

rggen-sample-testbench

rggen-vhdl

VHDL plugin for RgGen

rggen-sv-rtl

Common SystemVerilog RTL modules for RgGen

rggen-systemverilog

SystemVerilog RTL and UVM RAL model generators for RgGen

rggen-sample

rggen-sv-ral

UVM RAL class package for RgGen

rggen-verilog

Verilog writer plugin for RgGen

rggen-verilog-rtl

Common Verilog RTL modules for RgGen

rggen-c-header

C header file writer plugin for RgGen

rggen-core

RgGen Core Library

rggen-vhdl-rtl

rggen-duh

DUH support for RgGen

rggen-plugin-template

Project template for RgGen plugin

rggen-spreadsheet-loader

Spreadsheet loader for RgGen

rggen-default-register-map

Default Register Map Implementation for RgGen

rggen-docker

Docker image for RgGen

rggen-markdown

Markdown generator for RgGen

rggen-sample-plugin

Sample plugin project

rggen-checkout

rggen-devtools

rggen-release