firrtl

There are 4 repositories under firrtl topic.

chisel
chipsalliance / chisel
Chisel: A Modern Hardware Design Language
chip-generator chisel chisel3 firrtl rtl scala verilog
Language:Scala 3781
firrtl
chipsalliance / firrtl
Flexible Intermediate Representation for RTL
compiler firrtl hardware intermediate representation transformation
Language:Scala 703
ucsc-vama / essent
high-performance RTL simulator
chisel firrtl rtl scala
Language:Scala 117
freechipsproject / diagrammer
Provides dot visualizations of chisel/firrtl circuits
chisel chisel3 firrtl visualization
Language:Scala 112
librecores / riscv-sodor
educational microarchitectures for risc-v isa
chisel3 pynq-z1 arty tilelink librecores riscv scala firrtl
Language:Scala 62
scutdig / PyChip-py-hcl
A Hardware Construct Language
hardware-designs rtl verilog python python3 firrtl
Language:Python 39
grebe / ofdm
Chisel Things for OFDM
chisel chisel3 scala firrtl rtl chip-generator verilog
Language:Scala 29
IBM / chiffre
A fault-injection framework using Chisel and FIRRTL
chisel firrtl risc-v rocc rocket-chip fault-injection
Language:Scala 29
thoughtworks / hardposit-chisel3
Chisel library for Unum Type-III Posit Arithmetic
unum floating-point fpu chisel chisel3 scala firrtl verilog rtl posit
Language:Scala 29
hplp / aes_chisel
Implementation of the Advanced Encryption Standard in Chisel
aes advanced-encryption-standard chisel firrtl verilog rocc axi avalon parameterized
Language:Scala 19
CMU-SAFARI / Pythia-HDL
Implementation of Pythia: A Customizable Hardware Prefetching Framework Using Online Reinforcement Learning in Chisel HDL. To know more, please read the paper that appeared in MICRO 2021 by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).
prefetcher hdl scala chisel chisel3 firrtl firrtl-circuit reinforcement-learning machine-learning
Language:Scala 12
MaxXSoft / Bossa
BOOM's Simulation Accelerator.
boom rocket rocket-chip simulation chipyard accelerator chisel riscv risc-v rtl soc verilator firrtl
Language:Scala 11
chipsalliance / tree-sitter-firrtl
FIRRTL grammar for tree-sitter
tree-sitter parser firrtl
Language:C++ 8
MaxXSoft / Frenda
Split large FIRRTL into separated modules for incremental compilation.
firrtl chisel hardware compiler incremental-compilation
Language:Scala 8
IBM / firrtl-mode
Major mode for editing FIRRTL files in Emacs
firrtl emacs melpa
Language:Emacs Lisp 7
jkopanski / firrtl
Haskell FIRRTL implementation
firrtl hardware intermediate-representation
Language:Haskell 3
jpsety / obfuscation
A set of FIRRTL transforms for obfuscating circuits
chisel3 firrtl obfuscation
Language:Scala 0
tree-sitter-grammars / tree-sitter-firrtl
FIRRTL grammar for tree-sitter
firrtl parser tree-sitter
Language:C

firrtl

chipsalliance / chisel

chipsalliance / firrtl

ucsc-vama / essent

freechipsproject / diagrammer

librecores / riscv-sodor

scutdig / PyChip-py-hcl

grebe / ofdm

IBM / chiffre

thoughtworks / hardposit-chisel3

hplp / aes_chisel

CMU-SAFARI / Pythia-HDL

MaxXSoft / Bossa

chipsalliance / tree-sitter-firrtl

MaxXSoft / Frenda

IBM / firrtl-mode

jkopanski / firrtl

jpsety / obfuscation

tree-sitter-grammars / tree-sitter-firrtl