processor-design

There are 1 repository under processor-design topic.

darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
core cpu fpga processor processor-design risc-v riscv rtl rv32e rv32i softcore verilog
Language:Verilog 2149
eurorack-cpu
katef / eurorack-cpu
A CPU implemented in a modular synthesizer
modular synthesizer cpu-emulator processor-design
300
zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
adder alu cadence-virtuoso cpu instruction-set-architecture multiplier processor processor-design simd verilog verilog-project
Language:Verilog 128
peilin-chen / Zhulong-RISCV-CPU
CPU Design Based on RISCV ISA
integrated-circuits processor-design
Language:Verilog 81
shehanmunasinghe / tinyGPU
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
hdl computer-organization systemverilog processor-design gpu simd
Language:SystemVerilog 40
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 27
mpskex / chisel-npu
Chisel implementation of Neural Processing Unit for System on the Chip
chisel3 npu processor-design system-on-chip
Language:Scala 16
KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
EE577b-Course-Project
cadence-conformal cadence-ncverilog multiprocessor networkonchip processor-design synopsys-dc verilog-hdl
Language:Verilog 15
Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
engineering computer-engineering computer-science textbooks computer-organisation-architechure computer-organization computer-organisation computer-organization-lab computer-organization-and-design processor-architecture processor-design computer-organ ameythakur amey megasatish
Language:C 14
AnkurRyder / 8085-Processor
8-bit RISC Processor on Logisim
circuit-simulator logisim processor-design
13
darklife / udarkrisc
u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
core cpu fpga processor processor-design risc rtl softcore verilog
Language:Verilog 13
daniel-santos-7 / leaf
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
fpga fpga-soc processor-design risc-v riscv wishbone-bus
Language:VHDL 7
kara-abdelaziz / SEP-CPU
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
digital-design cpu processor-design processor processor-architecture processor-simulation computer-architecture computer-organization
Language:Assembly 6
rj45 / nanogo
NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs
compiler golang go homebrew-computer hobby-compiler hobby-language hobby-project cpu processor-design assembly
Language:Go 6
Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
bluespec bluespec-systemverilog bluespec-systemverilog-language processor-design processor-architecture vector-processor ram bus hardware hardware-designs hardware-acceleration processor vlsi-cad vlsi vlsi-physical-design vlsi-design
Language:Bluespec 6
JayKaku / RISC-V_MYTH_Workshop
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
risc-v riscv riscv32 riscv32i computer-architecture computer-hardware vlsi microprocessor tlv processor-design
Language:Python 5
lazyoracle / vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
fpga processor-simulator vhdl digital-electronics hdl hardware-description-language hardware-designs xilinx-fpga altera-fpga verilog vivado processor processor-architecture processor-design
Language:VHDL 5
Amir-Shamsi / Multicycle-MIPS-in-Verilog
MIPS Multicycle CPU design in Verilog
mips verilog multicycle-processor cpu processor-design datapath
Language:Verilog 4
Bennyaw / SimpleProcessor_Verilog
A simple processor designed using Verilog and Altera DE1 development board.
altera-de1 modelsim processor-design quartus simple verilog-hdl
Language:Verilog 4
LeviBohnacker / EDRICO
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and implement modern processor architectures.
risc-v risc-vcore processor-design 32-bit embedded
Language:VHDL 4
jakujobi / BitBlaster_10bit_Processor
Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
de10-lite digital-design fpga processor processor-design processors quartus quartus-prime systemverilog jakujobi
Language:SystemVerilog 2
lirui-shanghaitech / EE113_PROCESSOR
The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University
digital-design processor-design vlsi-design
2
streetdogg / mips-cpu
Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design
processor-design processor-architecture embedded-systems
Language:Verilog 2
0xD503 / ARM-Single-Cycle-Processor
ARM architecture single-cycle processor designed according to book "Digital design and computer architecture: ARM edition" as a practice in digital design.
processor-architecture processor-design arm embedded model-simulation
Language:SystemVerilog 1
Ajarlin / CS211-Computer-Architecture
Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.
c data-representation computer-arithmetic assembly-x86 digital-logic-design processor-design cache-design main-memory-design
Language:C 1
harmim / vut-inp-project2
Návrh počítačových systémů - Projekt 2 - Procesor s Harvardskou architekturou
vut inp fitkit vhld harvard processor processor-design
Language:C 1
helcsnewsxd / famaf-computer_science-computer_architecture-lab1
Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)
analysis armv8 assembly computer-architecture famaf-unc lab pipelined-processor processor-architecture processor-design python quartus university-project system-verilog hardware-description-language
Language:SystemVerilog 1
KonstantinosVasilopoulos / aueb_processor
A 16 bit processor, following the RISC architecture. Made with Quartus and VHDL.
vhdl alu processor processor-design quartus quartus2 16-bit risc-processor
Language:HTML 1
luisalejandrobf / BoothsAlgorithm
Implementation of Booth's algorithm for signed binary multiplication. It includes code designed for the PDUA processor, developed by the Pontificia Universidad Javeriana. The algorithm is provided in assembly language and includes its translation into executable binary instructions.
assembly-language binary binary-instructions booth-multiplier booth-s-algorithm booths-algorithm computer-architecture javeriana pdua pdua-processor processor-design signed-binary-multiplication
Language:Assembly 1
nayas360 / syn01
Custom processor implemented in logisim-evolution
processor processor-architecture processor-design processor-simulator assembler architecture
Language:Python 1
overengineer / SpecialPurposeProcessor
FPGA implementation of a special purpose processor that performs single operation using custom ALU. You can take look at the [related blog post] (https://overengineer.github.io/SpecialPurposeProcessor) for further details.
fpga processor-design verilog
Language:Verilog 1
seyang1 / pub-ips
systemverilog systemverilog-hdl verilog verilog-hdl asic asic-design riscv verilog-code verilog-components verilog-project openrisc gpgpu gpgpu-computing gpu-computing processor processor-architecture processor-design
1
tugrul512bit / AdvancedMacroDevices
2D RPG/RTS/Simulation game that lets you design a CPU & manage your corporation against other corporations.
architecture cpu cpu-design-game design game management processor-architecture processor-design processor-simulator rpg-game rts-game simulation
Language:C++ 1
Whitelisted2 / CS311-CompArch-Lab
This repository contains files related to Computer Architecture Lab (Autumn 2022).
assembler assembly-language discrete-event-simulation java l1-cache latency-analysis pipelining processor-design processor-simulator simulation single-cycle-processor toyrisc
Language:Java 1
vbogdev / vbn-Riscv
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
axi4 ddr3 fpga out-of-order processor processor-architecture processor-design processor-simulator risc-v superscalar superscalar-cpu
Language:SystemVerilog 0
AryaTopale / IPA
In this project, we have programmed a sequential as well as a pipelined processor architecture which includes fetch execute cycle. We have implemented this in Verilog.
processor processor-architecture processor-design verilog-hdl
Language:Verilog

processor-design

darklife / darkriscv

katef / eurorack-cpu

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

peilin-chen / Zhulong-RISCV-CPU

shehanmunasinghe / tinyGPU

alirezakay / RISC-CPU

mpskex / chisel-npu

KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

AnkurRyder / 8085-Processor

darklife / udarkrisc

daniel-santos-7 / leaf

kara-abdelaziz / SEP-CPU

rj45 / nanogo

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

JayKaku / RISC-V_MYTH_Workshop

lazyoracle / vhdl-processor

Amir-Shamsi / Multicycle-MIPS-in-Verilog

Bennyaw / SimpleProcessor_Verilog

LeviBohnacker / EDRICO

jakujobi / BitBlaster_10bit_Processor

lirui-shanghaitech / EE113_PROCESSOR

streetdogg / mips-cpu

0xD503 / ARM-Single-Cycle-Processor

Ajarlin / CS211-Computer-Architecture

harmim / vut-inp-project2

helcsnewsxd / famaf-computer_science-computer_architecture-lab1

KonstantinosVasilopoulos / aueb_processor

luisalejandrobf / BoothsAlgorithm

nayas360 / syn01

overengineer / SpecialPurposeProcessor

seyang1 / pub-ips

tugrul512bit / AdvancedMacroDevices

Whitelisted2 / CS311-CompArch-Lab

vbogdev / vbn-Riscv

AryaTopale / IPA