processor-design

There are 1 repository under processor-design topic.

darklife / darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
riscv processor-design rv32i rv32e verilog risc-v fpga rtl softcore core processor cpu
Language:Verilog 1900
eurorack-cpu
katef / eurorack-cpu
A CPU implemented in a modular synthesizer
cpu-emulator modular processor-design synthesizer
297
zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.
adder alu cadence-virtuoso cpu instruction-set-architecture multiplier processor processor-design simd verilog verilog-project
Language:Verilog 102
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 26
shehanmunasinghe / tinyGPU
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
hdl computer-organization systemverilog processor-design gpu simd
Language:SystemVerilog 21
Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
engineering computer-engineering computer-science textbooks computer-organisation-architechure computer-organization computer-organisation computer-organization-lab computer-organization-and-design processor-architecture processor-design computer-organ ameythakur amey megasatish
Language:C 14
KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip
EE577b-Course-Project
cadence-conformal cadence-ncverilog multiprocessor networkonchip processor-design synopsys-dc verilog-hdl
Language:Verilog 13
AnkurRyder / 8085-Processor
8-bit RISC Processor on Logisim
logisim circuit-simulator processor-design
12
darklife / udarkrisc
u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV
core cpu fpga processor processor-design risc rtl softcore verilog
Language:Verilog 11
rj45 / nanogo
NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs
assembly compiler cpu go golang hobby-compiler hobby-language hobby-project homebrew-computer processor-design
Language:Go 6
Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
bluespec bluespec-systemverilog bluespec-systemverilog-language processor-design processor-architecture vector-processor ram bus hardware hardware-designs hardware-acceleration processor vlsi-cad vlsi vlsi-physical-design vlsi-design
Language:Bluespec 6
daniel-santos-7 / leaf
Um pequeno processador RISC-V de 32 bits desenvolvido com a linguagem de descrição VHDL.
fpga fpga-soc processor-design risc-v riscv wishbone-bus
Language:VHDL 5
JayKaku / RISC-V_MYTH_Workshop
RV32I core using TL-Verilog.This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover
risc-v riscv riscv32 riscv32i computer-architecture computer-hardware vlsi microprocessor tlv processor-design
Language:Python 5
lazyoracle / vhdl-processor
An 8-bit processor in VHDL based on a simple instruction set
fpga processor-simulator vhdl digital-electronics hdl hardware-description-language hardware-designs xilinx-fpga altera-fpga verilog vivado processor processor-architecture processor-design
Language:VHDL 5
kara-abdelaziz / SEP-CPU
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
digital-design cpu processor-design processor processor-architecture processor-simulation computer-architecture computer-organization
Language:Assembly 4
LeviBohnacker / EDRICO
EDRICO (Educational DHBW RISC-V Core) is a small 32-bit RISC-V core implementing the Integer base architecture and Zicsr extension. It was developed as part of a students project at the DHBW Ravensburg by Noah Wölki and Levi Bohnacker. Future developments (outside of the scope of DHBW Ravensburg) are planned to add further ISA extensions and implement modern processor architectures.
32-bit embedded processor-design risc-v risc-vcore
Language:VHDL 4
Bennyaw / SimpleProcessor_Verilog
A simple processor designed using Verilog and Altera DE1 development board.
verilog-hdl processor-design simple altera-de1 modelsim quartus
Language:Verilog 2
jakujobi / BitBlaster_10bit_Processor
Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.
de10-lite digital-design fpga processor processor-design processors quartus quartus-prime systemverilog jakujobi
Language:SystemVerilog 2
lirui-shanghaitech / EE113_PROCESSOR
The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University
processor-design digital-design vlsi-design
2
streetdogg / mips-cpu
Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design
processor-design processor-architecture embedded-systems
Language:Verilog 2
0xD503 / ARM-Single-Cycle-Processor
ARM architecture single-cycle processor designed according to book "Digital design and computer architecture: ARM edition" as a practice in digital design.
arm embedded model-simulation processor-architecture processor-design
Language:SystemVerilog 1
Ajarlin / CS211-Computer-Architecture
Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.
c data-representation computer-arithmetic assembly-x86 digital-logic-design processor-design cache-design main-memory-design
Language:C 1
Amir-Shamsi / Multicycle-MIPS-in-Verilog
MIPS Multicycle CPU design in Verilog
cpu datapath mips multicycle-processor processor-design verilog
Language:Verilog 1
harmim / vut-inp-project2
Návrh počítačových systémů - Projekt 2 - Procesor s Harvardskou architekturou
vut inp fitkit vhld harvard processor processor-design
Language:C 1
krishnak1808 / pipe-MIPS32
It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.
processor-design verilog verilog-hdl verilog-project
Language:Verilog 1
luisalejandrobf / BoothsAlgorithm
Implementation of Booth's algorithm for signed binary multiplication. It includes code designed for the PDUA processor, developed by the Pontificia Universidad Javeriana. The algorithm is provided in assembly language and includes its translation into executable binary instructions. Instructions are available in English and Spanish.
binary booth-multiplier booths-algorithm javeriana pdua assembly-language computer-architecture processor-design binary-instructions booth-s-algorithm pdua-processor signed-binary-multiplication
Language:Assembly 1
mpskex / chisel-npu
Chisel implementation of Neural Processing Unit for System on the Chip
chisel3 npu processor-design system-on-chip
Language:Scala 1
nayas360 / syn01
Custom processor implemented in logisim-evolution
processor processor-architecture processor-design processor-simulator assembler architecture
Language:Python 1
overengineer / SpecialPurposeProcessor
FPGA implementation of a special purpose processor that performs single operation using custom ALU. You can take look at the [related blog post] (https://overengineer.github.io/SpecialPurposeProcessor) for further details.
fpga processor-design verilog
Language:Verilog 1
seyang1 / pub-ips
systemverilog systemverilog-hdl verilog verilog-hdl asic asic-design riscv verilog-code verilog-components verilog-project openrisc gpgpu gpgpu-computing gpu-computing processor processor-architecture processor-design
1
Subangkar / Computer-Architecture-CSE-306-BUET
Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET
mips-architecture mips mips-processor floating-point-arithmetic logisim simulation circuit-simulation 4-bit cpu 4-bit-cpu 16-bit-floating-point-adder alu processor-design processor-architecture registers computer-architecture buet cse-buet cse
Language:VHDL 1
tugrul512bit / AdvancedMacroDevices
2D RPG/RTS/Simulation game that lets you design a CPU & manage your corporation against other corporations.
architecture cpu cpu-design-game design game management processor-architecture processor-design processor-simulator rpg-game rts-game simulation
Language:C++ 1
Whitelisted2 / CS311-CompArch-Lab
This repository contains files related to Computer Architecture Lab (Autumn 2022).
assembler assembly-language discrete-event-simulation java l1-cache latency-analysis pipelining processor-design processor-simulator simulation single-cycle-processor toyrisc
Language:Java 1
yth98 / DSD_processor
A synthesizable pipelined RISC-V processor. (Digital System Design, Spring 2020, NTUEE)
processor-design risc-v
Language:Verilog 1
ttqureshi / 3-stage-pipelined-32-bit-Processor-RISC-V-ISA-
Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture
hdl processor-design processor riscv
Language:SystemVerilog
ttqureshi / 5-stage-pipelined-32-bit-Processor-RISC-V-ISA-
Implementing a 32-bit processor using RISC-V architecture.
hdl processor riscv32 processor-design
Language:SystemVerilog

processor-design

darklife / darkriscv

katef / eurorack-cpu

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

alirezakay / RISC-CPU

shehanmunasinghe / tinyGPU

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

KevinWang96 / Chip-Multi-processor-System-based-on-Cardinal-Bidirectional-Ring-Network-on-chip

AnkurRyder / 8085-Processor

darklife / udarkrisc

rj45 / nanogo

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

daniel-santos-7 / leaf

JayKaku / RISC-V_MYTH_Workshop

lazyoracle / vhdl-processor

kara-abdelaziz / SEP-CPU

LeviBohnacker / EDRICO

Bennyaw / SimpleProcessor_Verilog

jakujobi / BitBlaster_10bit_Processor

lirui-shanghaitech / EE113_PROCESSOR

streetdogg / mips-cpu

0xD503 / ARM-Single-Cycle-Processor

Ajarlin / CS211-Computer-Architecture

Amir-Shamsi / Multicycle-MIPS-in-Verilog

harmim / vut-inp-project2

krishnak1808 / pipe-MIPS32

luisalejandrobf / BoothsAlgorithm

mpskex / chisel-npu

nayas360 / syn01

overengineer / SpecialPurposeProcessor

seyang1 / pub-ips

Subangkar / Computer-Architecture-CSE-306-BUET

tugrul512bit / AdvancedMacroDevices

Whitelisted2 / CS311-CompArch-Lab

yth98 / DSD_processor

ttqureshi / 3-stage-pipelined-32-bit-Processor-RISC-V-ISA-

ttqureshi / 5-stage-pipelined-32-bit-Processor-RISC-V-ISA-