digital-logic

There are 4 repositories under digital-logic topic.

logisim-evolution
logisim-evolution / logisim-evolution
Digital logic design tool and simulator
logisim-evolution education circuit circuits digital-circuit digital-circuits simulator logic digital-logic digital-logic-design fpga timing-diagram logisim vhdl verilog
Language:Java 4766
tilk / digitaljs
Teaching-focused digital circuit simulator
simulator circuit-simulator logic-gates logic-circuit-simulator digital-logic
Language:JavaScript 654
TimRudy / ice-chips-verilog
IceChips is a library of all common discrete logic devices in Verilog
7400 digital-logic eda fpga icestorm iverilog logic-circuit open-hardware verilog-components
Language:Verilog 128
AnuragAnalog / GateResources
Here are my GATE CSE 2021 Resources
gate cse aptitude engineering-mathematics digital-logic coa programming data-structures algorithms theory-of-computation compiler-design os dbms cn 2021 resources
122
matijakevic / mcircuit
A digital logic simulator inspired by Logisim.
logisim digital-logic-simulator simulation simulator circuit-simulator circuit-simulation circuit digital-logic python python3 qt llvm llvmlite pyside pyside6 qt6 networkx
Language:Python 46
sabertazimi / hust-lab
Labs for Computer Science: C, Assembly, Data Structure, CSAPP, HSI, MATLAB, Digital Logic, Verilog, Compilers, Operating Systems
hust-lab hust lab computer-science algorithm assembly c compiler data-structrues digital-logic verilog functional-programming matlab operating-system
Language:C 29
LevKruglyak / CircuitSimulator
Simple Java application for simulating digital circuits
computer-engineering digital-logic java
Language:Java 28
fcayci / vhdl-digital-design
VHDL code examples for a digital design course
vhdl fpga digital-design digital-logic
Language:VHDL 20
Es1chUbJyan9 / 32bit_Quine-McCluskey_and_Petrick_Method_in_C
32bit Simplifier of Boolean functions
quine-mccluskey quine-mccluskey-algorithm petrick-method c digital-logic logic-programming simplification
Language:C 19
TimRudy / uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
digital-logic eda fpga icestorm iverilog open-hardware verilog-components hardware-designs serialport uart-interface uart-verilog
Language:Verilog 18
Aparnaraha / Gate2024
here the notes provided by the seniors who already cracked IITs as well as how much I'll cover for my exams I'll provide my notes as well. If you want you can access the course by these links also
algorithms aptitude compiler-design computer-networks computer-organisation-architechure data-structures database-management dbms digital-logic discrete-mathematics engineering-mathematics operating-system programming programming-in-c theory-of-computation toc gate gate-notes gate2024 graduate-aptitude-test
15
2catycm / SUSTech-CS202_214-Computer_Organization-Project
This is the mirror for gitee in github for project assignment of cs202 / 214 Computer Organization course of Southern University of Science and Technology， which is to manufacture a CPU. 这是南方科技大学CS202/214计算机组成原理课程的大作业——实现一个CPU。
computer-organization-and-design cpu digital-logic mips sustech-course-code
Language:Verilog 14
dramforever / finlog
Compiling finite generators to digital logic. WIP
verilog digital-logic compiler haskell
Language:Haskell 14
Multimedia-Processing / Digital-Logic-Design
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
vhdl learn fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 verilog hdl soc-kit altera-cyclone systemverilog xilinx xilinx-vivado xilinx-fpga altera-fpga altera-quartus digital-logic-design digital-logic vhdl-verilog digital verilog-hdl
Language:Verilog 14
chaseruskin / legoHDL
An experimental package manager and development tool for Hardware Description Languages (HDL).
package-manager hardware-description-language hdl hardware-design fpga verilog vhdl digital-design digital-logic
Language:Python 12
anuejn / XC9500
WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.
cpld yosys reverse-engineering digital-logic
Language:Python 10
WilliamYi96 / SimpleComputer
The design and implementation of simple computer by quartus.
computer digital-logic vhdl computer-design-and-implementation
Language:VHDL 9
xprova / xprova
Formal verification engine for Verilog with built-in support for simulating flip-flop metastability
formal-verification digital-logic verilog model-checking
Language:Java 9
DheerendraRathor / vhdl
This repository contains the codes for various type of circuits simulated in VHDL in Xilinx ISE Design.
digital-logic logic gates vhdl circuit-simulator
Language:VHDL 8
djcopley / QuineMcCluskey
A powerful tool for minimizing Boolean functions
digital-logic-simplification digital-logic minimization quine-mccluskey python3 boolean-algebra boolean-logic
Language:Python 8
bespoyasov / binary-full-adder-in-the-game-of-life
Binary adder implementation in the Game of Life written in JavaScript using canvas.
game-of-life digital-logic half-adder full-adder tutorial
Language:JavaScript 6
RyanAlameddine / WireFormSketch
Simulating hand drawn digital-logic circuit diagrams projected onto a sheet of paper!
opencv digital-logic circuits hand-drawn computer-vision logisim wireform
Language:C# 6
tuura / sync-models
Tool for creating synchronous models and behavioral specifications for asynchronous circuits
digital-logic asynchronous-circuits formal-verification model-checking verilog
Language:Verilog 6
rohityadav-sas / K-Map-Solver
The Karnaugh Map (KMap) Solver is a C++ application featuring a graphical interface for solving Karnaugh Maps. Users can interactively input values into a KMap grid and calculate corresponding minterms. The project aims to simplify Boolean expressions and visualize them using logic gates.
digital-logic karnaugh-map-solver k-map-solver raylib-cpp
Language:C++ 4
tinsir888 / nju-dlco-lecture
My solutions for DLCO(Digital Logic and Computer Organization) lecture assignments of NJU-ProjectN. DLCO is the bridging course for Project YSYX. Each lab eventually runs on NVBoard(another sub-project of NJU-ProjectN), a vitual FPGA.
computer-organization digital-logic verilog nvboard
Language:Makefile 4
twlite / digital-logic
A collection of digital logic utilities
api digital-logic hacktoberfest logic-gates
Language:TypeScript 4
danielkim802 / PyLogic
Python digital logic library
digital-logic digital-logic-design simulation
Language:Python 3
digital-logic-sim
lubinpappalardo / digital-logic-sim
Lubin Pappalardo's official Digital Logic Simulator.
digital-logic digital-logic-simulator html-css javascript jquery logic
Language:JavaScript 3
bryan-hoang / ELEC-271-Digital-Systems
VHDL Code for Labs done in a 2nd year Digital Systems course at Queen's University.
vhdl vhdl-code vhdl-coursework vhdl-examples digital-logic digital-logic-design digital-logic-simplification course coursework course-materials course-work
Language:VHDL 2
dakotacookenmaster / ByteWeave
ByteWeave is a web-based application that allows students to simulate digital circuits using a variety of logic gates, including AND, OR, NOT, NAND, NOR, INPUT, OUTPUT, and Seven Segment Displays. Instructors can also create assignments with custom logic circuits that are automatically graded.
autograding circuit-design digital-logic web-application
Language:TypeScript 2
FranMaric / diglog
Web app that helps you with subject "Digitalna logika" at FER. Check it out!
digital-logic boolean-algebra boolean-function boolean-function-minimizer
Language:Dart 2
namberino / nam85
An 8085-based Computer
computer-architecture digital-logic verilog 8085 fpga
Language:Verilog 2
tdepke2 / CircuitSim2
Graphical tool for developing and testing digital logic circuits from the gate level, built with C++ and SFML.
digital-logic computer-engineering circuit-simulation
Language:C++ 2
techcentaur / UART-Project
Universal Asynchronous Receiver-Transmitter. Semester project of Digital Logic and System Design course of fall 2017, IIT Delhi.
vhdl digital-logic iitd uart-interface
Language:VHDL 2
Tingwuren / BottlingTablets
北邮数字逻辑课程设计之药片管理系统
bupt course-design digital-logic
Language:VHDL 2
Tingwuren / ElectronicClock
北邮数字逻辑课程设计之电子钟
bupt course-design digital-logic
Language:VHDL 2

digital-logic

logisim-evolution / logisim-evolution

tilk / digitaljs

TimRudy / ice-chips-verilog

AnuragAnalog / GateResources

matijakevic / mcircuit

sabertazimi / hust-lab

LevKruglyak / CircuitSimulator

fcayci / vhdl-digital-design

Es1chUbJyan9 / 32bit_Quine-McCluskey_and_Petrick_Method_in_C

TimRudy / uart-verilog

Aparnaraha / Gate2024

2catycm / SUSTech-CS202_214-Computer_Organization-Project

dramforever / finlog

Multimedia-Processing / Digital-Logic-Design

chaseruskin / legoHDL

anuejn / XC9500

WilliamYi96 / SimpleComputer

xprova / xprova

DheerendraRathor / vhdl

djcopley / QuineMcCluskey

bespoyasov / binary-full-adder-in-the-game-of-life

RyanAlameddine / WireFormSketch

tuura / sync-models

rohityadav-sas / K-Map-Solver

tinsir888 / nju-dlco-lecture

twlite / digital-logic

danielkim802 / PyLogic

lubinpappalardo / digital-logic-sim

bryan-hoang / ELEC-271-Digital-Systems

dakotacookenmaster / ByteWeave

FranMaric / diglog

namberino / nam85

tdepke2 / CircuitSim2

techcentaur / UART-Project

Tingwuren / BottlingTablets

Tingwuren / ElectronicClock