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ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
Python interface and configurator for the ADI JESD204 Interface Framework
SpaceVNX (VITA 74.4) carrier based on Zynq-7000.
JESD204B ADC and DAC SYZYGY Pod.