Syntacore

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

scr1-sdk

open-source SDKs for the SCR1 core

snippy

libjaylink

Just a working copy of http://repo.or.cz/r/libjaylink.git

fpga-sdk-prj

FPGA-based SDK projects for SCRx cores

rvv-simulator

RISC-V vector extension ISA simulation

sc-bl

Syntacore first stage bootloader

openocd

OpenOCD Syntacore targets

riscv-binutils-gdb

RISC-V port of GDB

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

linux

boringssl

Mirror of BoringSSL

opensbi

riscv-clang

riscv-dbg-proposal

RISC-V Debug Specification update proposal

riscv-isa-manual

RISC-V Instruction Set Manual

riscv-v-spec

Working draft of the proposed RISC-V V vector extension

syntaj17

zephyr

Primary GIT Repository for the Zephyr Project

berkeley-softfloat-3

SoftFloat release 3

cs152-sp18-lab4

dining-philosophers

Simple c++11 demo of "Dining philosophers problem"

jimtcl

Official mirror of Jim Tcl, an open-source, small footprint implementation of Tcl

openssh-portable

Portable OpenSSH

openssl

TLS/SSL and crypto library

qemu

riscv-compliance

riscv-gcc

syntaj21

https://openjdk.org/projects/jdk-updates

tiny-dnn

header only, dependency-free deep learning framework in C++11