asip

There are 0 repository under asip topic.

neorv32
stnolting / neorv32
🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
risc-v soft-core vhdl fpga soc microcontroller processor cpu riscv system-on-chip embedded rv32 neorv32 asip rtos on-chip-debbuger smp multi-core hdl
Language:VHDL 1899
timurkelin / simsimd
Development and simulation framework for Application Specific Vector Processor
simd single-instruction-multiple-data asip application-specific architecture vector-processor cycle-accurate data-driven system-simulation systemc model-based dsp digital-signal-processing vector-core network-on-chip heterogeneous-structure heterogeneous-computing system-level-simulation multimode-processing simulation-framework
Language:C++ 16
nansencenter / sea_ice_type_cnn_training
Deep learning of satellite data: Use the data from satellites for machine learning (deep learning) purposes
tensorflow-training satellites asip tensorboard inference
Language:Jupyter Notebook 5
LatifAkcayGithub / PQC-ASIP
TTA-based ASIP designs for PQC algorithms
asip pqc tce tta
0
cepdnaclk / e19-4yp-RISC-V-Based-ASIP-for-Accelerating-DNA-Sequence-Alignment-on-Embedded-Systems
RISC-V based application-specific instruction set processor (ASIP) for Minimap2
asip bioinformatics-acceleration dna-sequence-alignment embedded-systems fpga genomic-computing hardware-acceleration minimap2 risc-v rocket-chip third-generation-sequencing
inhald / asip_stepper_motor_control
8-bit RISC ASIP for Stepper Motor Controller with both full and half step capabilities. Implemented in Verilog HDL.
asip risc-v stepper-motor-control verilog-hdl
Language:Verilog