processor-architecture

There are 11 repositories under processor-architecture topic.

intel / pcm
Intel® Performance Counter Monitor (Intel® PCM)
monitor-performance processor performance-monitoring energy performance-analysis performance-metrics performance-dashboard performance-visualization processor-architecture cpu xeon intel pcm power linux windows osx freebsd monitoring performance-counters
Language:C++ 3130
Ripes
mortbopet / Ripes
A graphical processor simulator and assembly editor for the RISC-V ISA
risc risc-v education simulator qt processor-architecture cpu-emulator computer-architecture
Language:C++ 3103
jbush001 / NyuziProcessor
GPGPU microprocessor architecture
fpga gpu-computing gpu verilog hardware microprocessor graphics processor-architecture
Language:C 2142
hlorenzi / customasm
💻 An assembler for custom, user-defined instruction sets! https://hlorenzi.github.io/customasm/web/
assembly assembly-language assembler instruction-set instruction-set-architecture processor-architecture microprocessor bytecode bytecode-compiler compiler customizable custom virtual-machine vm machine-code webassembly user-defined asm rust rust-lang
Language:Rust 998
RISC-V-Guide
mikeroyal / RISC-V-Guide
RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.
android-app computer-architecture cpu-profiling hypervisor optimize peripherals platformio processor processor-architecture risc-processor risc-v riscv riscv-emulator riscv64 rv32 sbc sel4 simulator tensoflow-lite virtualization
Language:Assembly 614
Mariotti94 / WebRISC-V
WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]
risc risc-v education simulator pipeline-simulation-environment processor-architecture computer-architecture php pipeline assembly
Language:PHP 155
jmuehlig / perf-cpp
Lightweight recording and sampling of performance counters for specific code segments directly from your C++ application.
cpp cpp17 library linux perf performance performance-monitoring system-programming performance-analysis performance-counters sampling performance-analyses performance-measurement performance-metrics processor-architecture instruction-based-sampling processor-event-based-sampling
Language:C++ 150
sstsimulator / sst-elements
SST Architectural Simulation Components and Libraries
simulator memory processor-architecture networking processor network-analysis cache cache-simulator trace system-design hpc simulation snl-other snl-performance-workflow
Language:C++ 102
HaDes-V
tscheipel / HaDes-V
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V processor using SystemVerilog and FPGA tools. Developed by TU Graz's EAS Group, this resource combines hands-on exercises in hardware/software co-design with practical implementation on the Basys3 FPGA board.
assembly-programming c-programming computer-architecture gtkwave hardware-software-codesign microcontroller-design open-educational-resources pipelines processor-architecture processor-design risc-v riscv rv32i system-verilog systemverilog university-course verilator vivado open-education
Language:SystemVerilog 86
caleb531 / cache-simulator
A processor cache simulator for the MIPS architecture
mips cache python processor processor-architecture simulator
Language:Python 40
alirezakay / RISC-CPU
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
cpu cpu-model cpu-architecture processor-design processor-architecture mips-processor isa instruction-set-architecture multi-cycle risc-processor vhdl vhdl-code vhdl-modules
Language:VHDL 29
physical-computation / sunflower-embedded-system-emulator
Sunflower Full-System Hardware Emulator and Physical System Simulator for Sensor-Driven Systems. Built-in architecture modeling of Hitachi SH (j-core), RISC-V, and more.
processor-simulator processor-architecture cross-compiler simulator embedded-systems emulators battery-simulator network-simulator power-simulator hitachi superh j-core riscv-simulator riscv-emulator riscv-sim riscv32 riscv
Language:C 29
sdasgup3 / parallel-processor-design
Super scalar Processor design
verilog-hdl processor verilog processor-architecture processor-simulator instruction-set-architecture superscalar pipeline-processor pipeline-cpu assembler flex bison parallel-computing instruction-level-parallelism mnemonics forwarding bypassing branch-prediction instruction-set opcode
Language:Verilog 21
Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB
CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>
engineering computer-engineering computer-science textbooks computer-organisation-architechure computer-organization computer-organisation computer-organization-lab computer-organization-and-design processor-architecture processor-design computer-organ ameythakur amey megasatish
Language:C 17
alexander-titov / public
A collection of my cources, lectures, articles and presentations
lectures presentations computer-science computer-architecture computer-engineering cpu processor-architecture digital-design
Language:C++ 16
ShichenQiao / ECE554_SP23_FPGA_Handwriting_Recognition
Senior Design Project at UW-Madison ECE
cnn fpga handwriting-recognition processor-architecture
Language:Verilog 15
GodTamIt / tomasulo-simulation
A simulation of the Tomasulo algorithm, a hardware algorithm for out-of-order scheduling and execution of computer instructions, written in C++.
tomasulo hardware simulation processor processor-architecture processor-simulator
Language:C++ 14
Mograsim
Mograsim-Team / Mograsim
Modular Graphical Simulator for Teaching Microprogramming
tum era am2900 amd microprogramming teaching assembler simulator modular graphical eclipse plugin processor processor-architecture processor-simulator instruction-set-architecture emulator mograsim java emulation
Language:Java 12
prantoamt / 16bit_processor_design
hardware-designs processor processor-architecture logisim computer-architecture simulation computer-design-and-implementation cpu cse332 cse mips mips-assembly mips-architecture mips-simulator mips-processor mips-assembler mips-language
12
GeekAlexis / superscalar-mips
A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines
processor-architecture verilog mips
Language:Verilog 11
aitesam961 / 16-Bit-RISC-Core-Processor
A RISC custom-ISA, 16-Bit Processor
cpu processor-architecture risc-v verilog assembly computer-architecture digital-design mips python
Language:Verilog 9
Danijel-Korent / RISC-V-emulator
RISC-V emulator/simulator in Python
bare-metal baremetal instruction-decoding python python3 risc-v riscv riscv-emulator riscv-linux riscv-simulator riscv32 system-emulation cpu cpu-simulator education processor-architecture risc-v-emulator risc-v-simulator rv32ima
Language:Python 8
digital-design-snu / RNBIP_SingleBusProcessor
Single Bus Processor - Summer Project 2016
processor processor-architecture processor-simulator fpga
Language:Verilog 8
luk3Sky / Building-A-Processor---Project
Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic
verilog-hdl verilog-project processor-architecture hdl alu
Language:Verilog 8
meiniKi / RV32I_SC_Logisim
A minimalistic single-cycle RISC-V platform for demonstrational and educational purposes in Logisim Evolution.
computer-science digital-design educational logisim logisim-evolution processor-architecture risc-v
Language:Verilog 8
pariyajebreili / 32BitMipsProcessor
An Implementation of MIPS processor with single cycle architecture using Verilog.
mips mips-assembly processor-architecture verilog
Language:Verilog 8
Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project
Domain Specific Hardware Accelerators - VLSI CAD Project
bluespec bluespec-systemverilog bluespec-systemverilog-language processor-design processor-architecture vector-processor ram bus hardware hardware-designs hardware-acceleration processor vlsi-cad vlsi vlsi-physical-design vlsi-design
Language:Bluespec 7
worthant / OPD
:computer: This course is about computer science basics.
computer-architecture-fundamentals microprocessors processor-architecture unix-like-os unix-os computer-science-basics
Language:Assembly 7
arda-guler / TurnaCore
An imaginary 16-bit CPU architecture with custom assembly language and instructions
assembly cpu cpu-emulator educational experimental low-level processor processor-architecture processor-simulator memory ram emulator asm challenge
Language:Python 6
arxiver / Pipelined-MIPS
MIPS Pipelined CPU simulation using VHDL language
hardware-designs processor processor-architecture processor-simulator vhdl vhdl-code
Language:VHDL 6
kara-abdelaziz / SEP-CPU
SEP, for Simple Enough Processor, is an elaborated from scratch simulated (on Logisim) educational CPU
digital-design cpu processor-design processor processor-architecture processor-simulation computer-architecture computer-organization
Language:Assembly 6
the-pinbo / MIPS-5-Stage-Pipeline-Project
This project involves the implementation and simulation of a MIPS 5-stage pipelined processor using Verilog. The implementation is based on the MIPS architecture as outlined in the "Computer Organization and Design: The Hardware/Software Interface" and "Digital Design and Computer Architecture"
computer-architecture fpga mips processor-architecture verilog
Language:Verilog 6
thenamangoyal / RISC-Simulator
A C++ pipeline based simulator of RSIC architecture.
risc-processor mem assembly risc-simulator pipeline-simulator risc-language architecture computer-architecture simplerisc-assembly-language simplerisc c-plus-plus c-plus-plus-11 functional-simulator pipeline-cpu pipelining pipeline functional simulator processor-architecture processor-simulator
Language:C++ 6
trexxet / virtaxy-vm
Flexible functional simulator and assembler for user-defined architectures
assembler cpu-emulator c code-generation processor-architecture
Language:C 6
linguini1 / gol-16
A custom 16-bit processor with a custom assembly language and emulator, based off of the ARM 32-bit processor.
arm-assembly arm-processor assembler assembly emulator hardware hardware-design processor processor-architecture processor-arm schematic
Language:C 5
maxislash / Tomasulo
Python simulator of Tomasulo algorithm
processor processor-architecture python tomasulo-algorithm
Language:Python 5

processor-architecture

intel / pcm

mortbopet / Ripes

jbush001 / NyuziProcessor

hlorenzi / customasm

mikeroyal / RISC-V-Guide

Mariotti94 / WebRISC-V

jmuehlig / perf-cpp

sstsimulator / sst-elements

tscheipel / HaDes-V

caleb531 / cache-simulator

alirezakay / RISC-CPU

physical-computation / sunflower-embedded-system-emulator

sdasgup3 / parallel-processor-design

Amey-Thakur / COMPUTER-ORGANIZATION-AND-ARCHITECTURE-AND-PROCESSOR-ARCHITECTURE-LAB

alexander-titov / public

ShichenQiao / ECE554_SP23_FPGA_Handwriting_Recognition

GodTamIt / tomasulo-simulation

Mograsim-Team / Mograsim

prantoamt / 16bit_processor_design

GeekAlexis / superscalar-mips

aitesam961 / 16-Bit-RISC-Core-Processor

Danijel-Korent / RISC-V-emulator

digital-design-snu / RNBIP_SingleBusProcessor

luk3Sky / Building-A-Processor---Project

meiniKi / RV32I_SC_Logisim

pariyajebreili / 32BitMipsProcessor

Sooryakiran / Domain-Specific-Hardware-Accelerator-VLSI-CAD-Project

worthant / OPD

arda-guler / TurnaCore

arxiver / Pipelined-MIPS

kara-abdelaziz / SEP-CPU

the-pinbo / MIPS-5-Stage-Pipeline-Project

thenamangoyal / RISC-Simulator

trexxet / virtaxy-vm

linguini1 / gol-16

maxislash / Tomasulo