There are 2 repositories under risc-cpu topic.
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
14-bit CPU implementation in Logisim. This is a 14-bit RISC CPU logisim implementation. All files are included in this single repository.
16-bit MIPS Processor from scratch in VHDL
Simple RISC CPU. 根据夏宇闻《Verilog数字系统设计教程》第2版17.1节简化RISC_CPU设计修改
A 32-bit single cycle RISC CPU based on Harvard architecture with no cache or pipeline, by having very simple and reduced instruction set it can be used for educational purpose.