timing-analysis

There are 1 repository under timing-analysis topic.

The-OpenROAD-Project / OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
opendb-database openroad lef verilog timing-analysis def eda rtl gdsii cpp tcl
Language:Verilog 2256
rokath / trice
🟢 super fast 🚀 and tiny 🐥 embedded device 𝘾 printf-like trace ✍ code, works also inside ⚡ interrupts ⚡ and real-time PC 💻 logging (trace ID visualization 👀)
trace instrumentation embedded logging real-time debugging monitoring diagnostics tool data-recording rtos multi-language-support compression timing-analysis time-measurement golang printf encryption serial c
Language:C 828
The-OpenROAD-Project / OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
eda rtl tcl def gdsii verilog openroad timing-analysis lef opendb-database
Language:Verilog 511
LukasHedegaard / pytorch-benchmark
Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption
pytorch benchmark deep-learning gpu jetson flops timing-analysis python
Language:Python 109
zslwyuan / AMF-Placer
AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
fpga mixed-size placement placer timing timing-analysis timing-driven
Language:C++ 106
bojackchen / digital-flow
This is a tutorial on standard digital design flow
timing-analysis verilog-hdl synopsys logic-synthesis synthesis
Language:Tcl 79
msrocean / Tik_Tok
This repository contains code and data for "Tik-Tok: The Utility of Packet Timing in Website Fingerprinting Attacks" paper, published in PETS 2020.
website-fingerprinting tor-network timing-analysis attacks privacy-enhancing-technologies tik-tok deep-learning machine-learning privacy
Language:Python 55
digaryfa / UTH-Timer
Gate-level timing estimation toolkit
timing-analysis ccs effective-capacitance shielding-effect miller-effect
Language:Shell 25
paripath / cdf
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
characterization vlsi-circuits vlsi-design timing-analysis power-analysis hspice spice-simulator vlsi-cad
Language:C++ 13
typinghard / azure-devops-tracker
A NuGet that allows you to use a Azure DevOps Service Hook to track workitems changes in a simply and detailed way.
azure azuredevops tracker trackers scrum workitem columns agile-development agile team team-performance timing-analysis azure-devops devops
Language:C# 13
tu-dortmund-ls12-rt / SSSEvaluation
Evaluation Framework for Self-Suspending Task Systems
framework self-suspension timing-analysis
Language:Python 10
mkogax / GG_for_Arduino
GG for Arduino is a serial console library. It also contains various functions for implementing the console, for example printf(). You can implement a command line interface on your Arduino and add your own commands. This library contains built-in commands that allow memory access and timing analysis.
arduino cli command-line-interface console embedded printf timing-analysis
Language:C 9
os-fpga / Backend
Compiler backend from packing to bitstream generation.
bitstream-generation fpga-complete-flow packing placement routing sw timing-analysis
Language:C++ 7
lip6 / tas-yagle
Static Timing Analyser (LIP6)
eda timing-analysis
Language:C 5
Stubxnet / ttcp
ttcp is a simple Rust-coded tool to measure TCP timing and detect anomalies.
tcp timing-analysis
Language:Rust 2
pulsar-nulling
cgobat / pulsar-nulling
Analysis of radio pulsar parameters and their relationships with nulling statistics
pulsars catalogs astrophysics timing-analysis
Language:Jupyter Notebook 1
hansand02 / Sorteringsalgoritmer
Implementation of various sorting algorithms | python3
analysis-of-algorithms automated-testing mergesort quicksort timing-analysis
Language:Python 1
himelbrand / dns-timing
This is a collection of scripts that is used to time DNS queries using BIND, and create DNS access traces with hit and miss times (cache hit and miss that is)
dns bind traces timing-analysis
Language:Python 1
lukita69 / aes-prime-probe-key-recovery
A side-channel analysis project implementing a Prime+Probe cache attack to recover AES encryption keys by analyzing first-round T-table accesses. Includes parallelized data processing, statistical analysis, and heatmap visualization.
aes cache-attack cpa cryptanalysis csv gzip key-recovery matplotlib multiprocessing mutual-information numpy plotly python seaborn side-channel-analysis timing-analysis tqdm high-nibble prime-and-probe
Language:Python 1
mannan-wadhwa / mealy-fsm-2s-complement
Implements a Mealy FSM that computes the 2’s complement of a serial binary input, showcasing the full hardware design workflow from logic to gate-level simulation.
end-to-end post-synthesis rtl-design synthesis timing-analysis verification verilog verilog-project
Language:Verilog 1
mkogax / GG_for_CCRX
GG はシリアルコンソールを実現するための支援ライブラリです。コンソールを組み込むための補助的なツール（例えば書式付出力や文字列変換）を含みます。 GG for CCRX はルネサス RX でのポーティング例です。
cli console renesas-rx command-line-interface embedded printf timing-analysis
Language:C 1
PokeyMystery / SerDes-Design-UVM-and-Physical-Design
SerDes RTL design, verification using UVM and Physical design.
encoder-decoder fsm highspeed physical-design piso-shift-register place-and-route serdes sipo synthesis timing-analysis
Language:Verilog 1
rpigor / TPSim
TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
eda power-analysis simulator timing-analysis verilog
Language:C++ 1
tu-dortmund-ls12-rt / end-to-end
RTAS 2021 - Artifact Evaluation for "Timing Analysis of Asynchronized Distributed Cause-Effect Chains"
real-time timing-analysis end-to-end simulation-framework
Language:Python 1
afairless / asynchronous_downloads
Modular Python functions for asynchronous downloads
aiohttp asynchronous asynchronous-programming asyncio bytearray csv-files download functional-programming python python3 speedrun speedtest timing-analysis
Language:Python 0
caravagnalab / tickTack
Pseudo-timing copy number alterations in cancer
copy-number-variations somatic-mutations timing-analysis
Language:R 0
foRMA
CARV-ICS-FORTH / foRMA
foRMA is a python-based scripted tool that uses SST Dumpi traces to derive a profile of timing, data transfers, data transfer volume etc., for MPI RMA operations.
mpi-rma profiling timing-analysis trace-analysis
Language:Python 0
danielbboy111 / CPEN-311
CPEN 311: Digital Systems Design
arithmetic-circuits asynchronous-circuits combinational-logic fpga gpu-architecture ic-design mps pipelining sequential-circuits timing-analysis datapath-cirucits vhdl-synthesizable
0
deyatallman / Largest-Number-Solver
A program that determines the largest number possible from the contents of a given integer array. The array contents should be appended to each other in any order to form the largest number possible. For example, given the array { 11, 67, 79, 7, 22, 13 }, the largest number that it is possible is 79767221311
comparator generic-programming insertion-sort java timing-analysis
Language:Java 0
Interactive-Lightcurve-Explorer
fedefoga / Interactive-Lightcurve-Explorer
This repository contains an interactive lightcurve tool for xray timing analysis.
heasarc python3 stingray timing-analysis
Language:Python 0
himanshu5-prog / static_timing_analysis
This repo implements VLSI static timing analysis using C++.
graph-algorithms static-timing-analysis topological-sort vlsi vlsi-cad timing-analysis
Language:C++ 0
SARTHAK-JAIN-ASIC / EE533
This repository is for all the projects I did as research assistant under Prof. Young Cho and class EE533 @USC
computer-architecture fpga netfpga rtl-design timing-analysis verilog-hdl
Language:Perl 0
Compcode1 / nmap-automation
This project automates Nmap scans at scheduled intervals to analyze network activity over time.
automation cybersecurity nmap python scripts timing-analysis
Language:Python
weinbergerlab / RSVtiming
This repository contains the code and data required to perform the analysis for the manuscript https://doi.org/10.1101/2021.09.22.21256632
rsv epidemics spatial-analysis timing-analysis
Language:R
yasnakateb / AdaptiveClockManagement
⏳ Adaptive Clock Management in FPGAs Using Binary Search
adaptive-systems binary-search clock clock-divider digital-design fpga fsm hardware-design systemverilog timing-analysis clock-management
Language:SystemVerilog
yasnakateb / MultiClockSynchronization
⏰ Fpga Multi Clock Synchronization
clock fpga multi-clock producer-consumer systemverilog cdc clock-generator clock-synchronization mmcm clock-management digital-design hardware-design timing-analysis
Language:SystemVerilog

timing-analysis

The-OpenROAD-Project / OpenROAD

rokath / trice

The-OpenROAD-Project / OpenROAD-flow-scripts

LukasHedegaard / pytorch-benchmark

zslwyuan / AMF-Placer

bojackchen / digital-flow

msrocean / Tik_Tok

digaryfa / UTH-Timer

paripath / cdf

typinghard / azure-devops-tracker

tu-dortmund-ls12-rt / SSSEvaluation

mkogax / GG_for_Arduino

os-fpga / Backend

lip6 / tas-yagle

Stubxnet / ttcp

cgobat / pulsar-nulling

hansand02 / Sorteringsalgoritmer

himelbrand / dns-timing

lukita69 / aes-prime-probe-key-recovery

mannan-wadhwa / mealy-fsm-2s-complement

mkogax / GG_for_CCRX

PokeyMystery / SerDes-Design-UVM-and-Physical-Design

rpigor / TPSim

tu-dortmund-ls12-rt / end-to-end

afairless / asynchronous_downloads

caravagnalab / tickTack

CARV-ICS-FORTH / foRMA

danielbboy111 / CPEN-311

deyatallman / Largest-Number-Solver

fedefoga / Interactive-Lightcurve-Explorer

himanshu5-prog / static_timing_analysis

SARTHAK-JAIN-ASIC / EE533

Compcode1 / nmap-automation

weinbergerlab / RSVtiming

yasnakateb / AdaptiveClockManagement

yasnakateb / MultiClockSynchronization