There are 1 repository under timing-analysis topic.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
🟢 super fast 🚀 and tiny 🐥 embedded device 𝘾 printf-like trace ✍ code, works also inside ⚡ interrupts ⚡ and real-time PC 💻 logging (trace ID visualization 👀)
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
Easily benchmark PyTorch model FLOPs, latency, throughput, allocated gpu memory and energy consumption
AMF-Placer 2.0: An open-source timing-driven analytical mixed-size FPGA placer of heterogeneous resources (LUT/FF/LUTRAM/MUX/CARRY/DSP/BRAM...)
This is a tutorial on standard digital design flow
This repository contains code and data for "Tik-Tok: The Utility of Packet Timing in Website Fingerprinting Attacks" paper, published in PETS 2020.
Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
A NuGet that allows you to use a Azure DevOps Service Hook to track workitems changes in a simply and detailed way.
Evaluation Framework for Self-Suspending Task Systems
GG for Arduino is a serial console library. It also contains various functions for implementing the console, for example printf(). You can implement a command line interface on your Arduino and add your own commands. This library contains built-in commands that allow memory access and timing analysis.
Analysis of radio pulsar parameters and their relationships with nulling statistics
Implementation of various sorting algorithms | python3
This is a collection of scripts that is used to time DNS queries using BIND, and create DNS access traces with hit and miss times (cache hit and miss that is)
A side-channel analysis project implementing a Prime+Probe cache attack to recover AES encryption keys by analyzing first-round T-table accesses. Includes parallelized data processing, statistical analysis, and heatmap visualization.
Implements a Mealy FSM that computes the 2’s complement of a serial binary input, showcasing the full hardware design workflow from logic to gate-level simulation.
GG はシリアルコンソールを実現するための支援ライブラリです。コンソールを組み込むための補助的なツール(例えば書式付出力や文字列変換)を含みます。 GG for CCRX は ルネサス RX でのポーティング例です。
SerDes RTL design, verification using UVM and Physical design.
TPSim (Timing and Power Simulator) is a gate-level circuit simulator with timing and power estimation capabilities
RTAS 2021 - Artifact Evaluation for "Timing Analysis of Asynchronized Distributed Cause-Effect Chains"
Modular Python functions for asynchronous downloads
Pseudo-timing copy number alterations in cancer
foRMA is a python-based scripted tool that uses SST Dumpi traces to derive a profile of timing, data transfers, data transfer volume etc., for MPI RMA operations.
CPEN 311: Digital Systems Design
A program that determines the largest number possible from the contents of a given integer array. The array contents should be appended to each other in any order to form the largest number possible. For example, given the array { 11, 67, 79, 7, 22, 13 }, the largest number that it is possible is 79767221311
This repository contains an interactive lightcurve tool for xray timing analysis.
This repo implements VLSI static timing analysis using C++.
This repository is for all the projects I did as research assistant under Prof. Young Cho and class EE533 @USC
This project automates Nmap scans at scheduled intervals to analyze network activity over time.
This repository contains the code and data required to perform the analysis for the manuscript https://doi.org/10.1101/2021.09.22.21256632
⏳ Adaptive Clock Management in FPGAs Using Binary Search
⏰ Fpga Multi Clock Synchronization