xilinx-fpga

There are 29 repositories under xilinx-fpga topic.

openwifi
open-sdr / openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
fpga ofdm 802-11 zynq linux xilinx analog-devices mac80211 csma dma verilog hls openwifi ad9361 sdr software-defined-radio ieee80211 wifi xilinx-fpga hardware
Language:C 3762
prjxray
f4pga / prjxray
Documenting the Xilinx 7-series bit-stream format.
fpga xilinx xilinx-fpga artix artix7 kintex7 bitstream tools toolchain fuzzer vivado symbiflow
Language:Python 750
f4pga-arch-defs
f4pga / f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
fpga ice40 sphinx documentation verilog hdl xilinx-fpga artix kintex7 architecture-definitions verilog-simulator vpr primitives lattice toolchain synthesis python artix7 verilog-simulations symbiflow
Language:Jupyter Notebook 267
fpgasystems / Coyote
Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.
fpga hbm rdma service tcp virtualization amd xilinx-fpga gpu
Language:SystemVerilog 204
blaze
ingonyama-zk / blaze
blaze is a Rust library for ZK acceleration on Xilinx FPGAs.
aws fpga hardware zero-knowledge xilinx-fpga
Language:Rust 138
ultraembedded / openlogicbit
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
fpga logic-analyzer xilinx-fpga lattice-fpga altera-fpga ftdi232h ftdi2232h digital-signal-analyzer verilog
Language:Verilog 110
triSYCL / sycl
SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
xilinx-fpga xilinx-vitis trisycl oneapi-dpc sycl-compilation accelerators clang llvm dpc-toolchain cpp20 sycl
107
derekmulcahy / xvcpi
Xilinx Virtual Cable Server for Raspberry Pi
jtag zynq snickerdoodle xilinx-vivado xilinx-fpga
Language:C 106
yosys-f4pga-plugins
chipsalliance / yosys-f4pga-plugins
Plugins for Yosys developed as part of the F4PGA project.
yosys yosys-plugin eda fpga xilinx xilinx-fpga toolchain f4pga
Language:Verilog 84
ultraembedded / core_ft60x_axi
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
ftdi-devices ft600 axi4 bus-master verilog fpga xilinx-fpga data-acquisition usb3
Language:C++ 82
ultraembedded / core_dvi_framebuffer
Minimal DVI / HDMI Framebuffer
hdmi dvi verilog fpga xilinx-fpga video framebuffer axi4
Language:Verilog 74
f4pga / prjuray
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
fpga xilinx xilinx-fpga ultrascale ultrascale-plus bitstream fuzzer vivado symbiflow
Language:SystemVerilog 70
prjxray-db
f4pga / prjxray-db
Project X-Ray Database: XC7 Series
fpga xilinx xilinx-fpga artix artix7 kintex7 bitset tools toolchain database prjxray symbiflow
Language:Shell 62
diogofferreira / fpga-miner
:moneybag: A simplified version of an FPGA bitcoin miner :moneybag:
fpga bitcoin-miner xilinx-fpga vivado
Language:VHDL 48
pontazaricardo / Verilog_Calculator_Matrix_Multiplication
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
verilog vhdl calculator matrix-multiplication xilinx xilinx-ise xilinx-vivado xilinx-fpga low-level-programming hardware-designs ic-design
Language:Verilog 46
fredrequin / verilator_xilinx
Re-coded Xilinx primitives for Verilator use
fpga verilator verilog xilinx-fpga
Language:Verilog 37
ingonyama-zk / open-binius
building blocks for accelerating ZK proofs over binary fields
cryptography fpga hardware xilinx-fpga zero-knowledge
Language:Verilog 35
stevenbell / csirx
Open-source CSI-2 receiver for Xilinx UltraScale parts
mipi-camera csi2 xilinx-fpga ultrascale
Language:Verilog 34
sailordiary / computer-systems-ucas
**科学院大学计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
verilog cpu xilinx-vivado xilinx-fpga computer-systems
Language:Verilog 29
hex-five / multizone-fpga
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW platform for its MultiZone Trusted Execution Environment and MultiZone Trusted Firmware. The X300 is an enhanced secure version of the SiFive's Freedom E300 built around the Rocket chip developed at U.C. Berkeley.
risc-v rocket-chip fpga fpga-soc xilinx xilinx-fpga e300 bitstream digilent sifive-freedom arty-a7 artix-35t artix-100t sifive
Language:Scala 28
olivier-le-sage / camera-filters
Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.
sea-s7 fpga verilog mipi hdmi yuv2rgb rgb2yuv gamma-correction piecewise-linear-approximation spartan7 xilinx-fpga
Language:VHDL 28
KarenOk / SAP-1-Computer
Design and Implementation of a Simple-As-Possible 1 (SAP-1) Computer using an FPGA and VHDL.
vhdl fpga vivado xilinx-fpga
Language:VHDL 24
mcagriaksoy / VHDL-FPGA-LAB_PROJECTS
My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
xilinx-fpga xilinx-ise fpga vhdl vhdl-code vhdl-examples fpga-soc verilog
Language:VHDL 23
verilog-rle
geraked / verilog-rle
Verilog Implementation of Run Length Encoding for RGB Image Compression
verilog fpga ise rle rle-compression-algorithm compression-algorithm verilog-hdl verilog-code image-compression matlab fpga-programming xilinx xilinx-fpga run-length-encoding image-processing geraked rabist student-project yazd-university computer-engineering
Language:Verilog 22
sarthak268 / Embedded_Logic_and_Design
This repository contains all labs done as a part of the Embedded Logic and Design course.
verilog verilog-hdl verilog-programs verilog-project embedded-systems embedded-logic logic-circuit logic-programming embedded-c c vhdl vhdl-code zedboard xilinx xilinx-vivado xilinx-fpga xilinx-sdk arm vivado pmod
22
hex-five / multizone-iot-sdk
MultiZone® Trusted Firmware is the quick and safe way to build secure IoT applications with any RISC-V processor. It provides secure access to commercial and private IoT clouds, real-time monitoring, secure boot, and remote firmware updates. The built-in Trusted Execution Environment provides hardware-enforced separation ...
iot firmware mqtt tls tcp-ip tee trusted-execution-environment trustzone multizone lwip mbedtls freertos risc-v secure-boot embedded-systems ota-firmware-updates xilinx-fpga root-of-trust attestation digilent-arty-board
Language:C 19
Wissance / QuickSPI
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-hdl spi axi spi-ip-core spi-pld spi-fpga spi-interface verilog-spi axi-interfaces bit-oriented-spi soft-spi hard-spi dragster-spi fpga xilinx-fpga xilinx-vivado altera verilog-snippets verilog-hdl verilog-components
Language:Verilog 19
splAcharya / DigitalOscilloscope_Zynq7000Soc
A digital Oscilloscope designed using Zedboard (Zynq7000Soc). The input signal is sample and processed using Zedboard and the sample data is displayed using a Graphical User Interface which mimics an Oscilloscope.
zedboard digital-oscilloscope xilinx-fpga xilinx-vivado zynq-7000 fpga-soc verilog-hdl embedded-systems
15
theshadowx / keyboard-ip
PS/2 Keyboard IP written in VHDL for Xilinx FPGA
vhdl xilinx keyboard-ip xilinx-fpga demo
Language:VHDL 15
SalvatoreBarone / CNN-VHDL
A library of VHDL components for Neural Networks
artificial-intelligence artificial-neural-networks convolutional-neural-networks lenet-5 vhdl ghdl xilinx-fpga virtex approximation approximate-computing approximate-algorithms
Language:C++ 14
ilyajob05 / verilog_modules
verilog modules
7-segment fpga i2c memory nexys-4-spartan-3e nexys4 nexys4-board pll rmii spi synchronization timer uart usart verilog xilinx xilinx-fpga
Language:Verilog 12
merlin
mattuna15 / merlin
Learn how to create your own 32-bit system from scratch.
68000 68k 68k-assembly gcc-cross-compiler hardware fpga xilinx-fpga vivado arty digilent gameduino retrogaming
Language:Assembly 12
mcedrdiego / Kria_yolov3_ppe
Xilinx Kria KV260 Real-time PPE detection
yolov3 fpga xilinx-fpga real-time kria-som kv260
Language:C++ 12
Multimedia-Processing / Digital-Logic-Design
透過數位邏輯結合VHDL與Verilog的過程，作為從基礎數位邏輯到計算機系統結構，並實作出一顆CPU的教學書籍，希望未來可以成為教學範例檔案。目前將開發轉移到GitLab，因為可以呈現數學與MUL圖。
vhdl learn fpga altera-cyclone-v-sockit altera-cyclone-iii-de0 verilog hdl soc-kit altera-cyclone systemverilog xilinx xilinx-vivado xilinx-fpga altera-fpga altera-quartus digital-logic-design digital-logic vhdl-verilog digital verilog-hdl
Language:Verilog 12
santifs / ultrasonic-sensor
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
vhdl nexys4ddr fpga-programming xilinx-fpga vhdl-modules vhdl-code ultrasonic-sensor parking-sensor 7segment
Language:VHDL 12
SimpleSoC
siorpaes / SimpleSoC
Very simple Cortex-M1 SoC design based on ARM DesignStart
soc arm cortex-m xilinx-fpga xilinx-vivado designstart digitaldesign systemonchip fpga-soc fpga cortex-m1 hardware-designs verilog mcu
Language:C 12

xilinx-fpga

open-sdr / openwifi

f4pga / prjxray

f4pga / f4pga-arch-defs

fpgasystems / Coyote

ingonyama-zk / blaze

ultraembedded / openlogicbit

triSYCL / sycl

derekmulcahy / xvcpi

chipsalliance / yosys-f4pga-plugins

ultraembedded / core_ft60x_axi

ultraembedded / core_dvi_framebuffer

f4pga / prjuray

f4pga / prjxray-db

diogofferreira / fpga-miner

pontazaricardo / Verilog_Calculator_Matrix_Multiplication

fredrequin / verilator_xilinx

ingonyama-zk / open-binius

stevenbell / csirx

sailordiary / computer-systems-ucas

hex-five / multizone-fpga

olivier-le-sage / camera-filters

KarenOk / SAP-1-Computer

mcagriaksoy / VHDL-FPGA-LAB_PROJECTS

geraked / verilog-rle

sarthak268 / Embedded_Logic_and_Design

hex-five / multizone-iot-sdk

Wissance / QuickSPI

splAcharya / DigitalOscilloscope_Zynq7000Soc

theshadowx / keyboard-ip

SalvatoreBarone / CNN-VHDL

ilyajob05 / verilog_modules

mattuna15 / merlin

mcedrdiego / Kria_yolov3_ppe

Multimedia-Processing / Digital-Logic-Design

santifs / ultrasonic-sensor

siorpaes / SimpleSoC