uart-verilog

There are 8 repositories under uart-verilog topic.

pConst / basic_verilog
Must-have verilog systemverilog modules
fpga delay debounce encoder xilinx altera verilog fifo tcl spi-master synchronizer pwm uart uart-protocol uart-verilog uart-tx uart-receiver uart-controller spi-interface hls
Language:Verilog 1866
ZipCPU / wbuart32
A simple, basic, formally verified UART controller
fpga uart uart-verilog verilator wishbone wishbone-bus verilog serialport
Language:Verilog 313
ben-marshall / uart
A simple implementation of a UART modem in Verilog.
hardware fpga verilog verilog-hdl uart uart-verilog
Language:Verilog 163
halftop / Interface-Protocol-in-Verilog
Interface Protocol in Verilog
verilog-hdl uart-protocol uart-verilog spi
Language:Verilog 50
TimRudy / uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
digital-logic eda fpga icestorm iverilog open-hardware verilog-components hardware-designs serialport uart-interface uart-verilog
Language:Verilog 36
GLADICOS / UART
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
systemc systemc-model uart-verilog gtkwave icarus-verilog uart dut
Language:Verilog 7
addisonElliott / LogiFindFPGATest
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
altera quartus-prime logifind fpga verilog verilog-hdl uart-verilog nec-verilog ir-receiver cyclone-iv 7-segment buzzer ep4ce6e22c8n pl2303 easyfpga
Language:Verilog 6
yasnakateb / UARTCommunication
☎️ UART Communication Implementation in Verilog HDL
verilog iverilog icarus-verilog uart uart-verilog uart-interface uart-protocol serial-communication
Language:Verilog 5
kishanpatelec / UART-for-bluetooth-module
uart uart-verilog uart-controller uart-com uart-protocol uart-tx uart-receiver bluetooth hc-05
Language:Verilog 4
Shubhayu-Das / VL504-project
Displaying images taken from an OV7670/laptop camera
vga basys3 ov7670 uart-verilog
Language:Python 3
AhmedSobhy01 / uart-verilog
Synthesizable Verilog implementation of the classic UART 16550 serial interface implements configurable baud rate, FIFO buffering, parity, error detection, and testbenches for simulation
16550 fifo hardware-designs modelsim questasim serial-communication simulation uart uart-verilog verilog
Language:Verilog 2
KelvinThomasYB17 / Transferring-data-from-SPI-to-UART-using-BMP280-sensor-with-Verilog
Transferring data from SPI to UART using BMP280 sensor with Verilog
bmp280 spi spi-protocol uart-protocol uart-verilog verilog spi-verilog de10-lite fpga modelsim
Language:Verilog 2
KevinWang96 / UART_Verilog_Based
Verilog Modeling of UART Tx and Rx
uart-protocol uart-verilog verilog-hdl
Language:Verilog 2
mwbryant / uart-CI
Basic continous integration testing for verilog projects
verilator verilog fpga uart-verilog uart uart-tx
Language:C++ 2
TheLeopardsH / UART
Universal Asynchronous Receiver Transmitter
uart uart-verilog uart-receiver verilog fpga receiver-transmitter
Language:Verilog 2
Wissance / QuickRS232
A versatile full-duplex RS232 FPGA module with internal FIFO buffer on RX
fpga fpga-programming rs232 verilog-library serial-communication fpga-rs232 serial-communication-fpga verilog-rs232 verilog-serial-port altera-uart uart uart-verilog verilog-uart
Language:Verilog 2
Abd-El-Rahman-Sabry / processing-unit-with-uart
This project implements a UART-controlled processing unit with dual clock domains for UART communication and datapath operations. A state machine decodes serial commands to control the datapath, enabling ALU operations, register file access, and data transmission. It's designed for embedded systems and educational purposes.
processor processor-architecture uart uart-verilog
Language:Verilog 1
BrunoBMoura / BM_CORE
Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.
mips architecture risc-processor uart uart-verilog operating-system
Language:Verilog 1
ColtonBeery / UART_TX
Basys 3 UART Tx for COMPE470L class
uart-tx verilog uart-verilog basys3-fpga
Language:Verilog 1
djkabutar / test_mipi_encoder_decoder
MIPI to multiple peripheral (UART, I2C, SPI, 1-Wire)
mipi uart-verilog verilog
Language:Verilog 1
Fahad-Habib / UART-Tx
UART Tx implemented in SystemVerilog from scratch.
digital-system-design uart uart-verilog
Language:SystemVerilog 1
meeeeet / UART-DesignAndVerification
rtl-design-and-verification serial-communication systemverilog uart uart-verilog
Language:SystemVerilog 1
sidhantp1906 / UART
UART implementation using Verilog HDL
uart-protocol uart-verilog verilog xilinx-ise xilinx-fpga rtl
Language:Verilog 1
STjurny / BasicUART
Small light-weight implementation of UART in Verilog.
verilog uart uart-verilog fpga ice40 tinyfpga alchitry serialport
Language:Verilog 1
2uger / verilog_uart_hw
Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board
cocotb uart verilog fpga hardware uart-verilog xilinx-fpga combinational-logic finite-state-machine
Language:Python 0
fscatox / efes_prj
FPGA + STM32 stepper motor controller with programmable movement pattern, PS/2 keyboard interface, and non-volatile pattern storage. Toy system developed for the "Electronics for Embedded Systems" course at PoliTO
bipolar-stepper-motor fifo-verilog ps2-controller spi-verilog stm32 systemverilog uart-verilog
Language:C++ 0
hl271 / uart_with_fifo
Verilog implementation of UART protocol with integrated FIFO buffer
fifo uart uart-verilog verilog
Language:Verilog 0
PhatLe15 / Computer-Architecture-Design
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.
mips-processor soc fpga-validation performance-analysis truth-tables uart-verilog
Language:HTML 0
sushi0706 / uart
verilog-uart
uart-protocol uart-verilog verilog modelsim uart-rx uart-tx
Language:Verilog 0
0marAmr / UART-Interface
Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL
communication-interface digital-design uart-interface uart-rx uart-tx uart-verilog
Language:Verilog
DatNT018 / FPGA-UART-Transceiver
UART communication link between two Altera Board (DE2-115)
de2-115 fpga uart-verilog verilog
Language:Verilog
DatNT018 / fpga-verilog-modules
fpga modules
fpga-programming i2c protocol spi-verilog uart-verilog verilog
Language:Verilog
mengstr / vuart
WIP - Smallish UART written in Verilog
verilog uart uart-verilog wip-do-not-use
Language:Verilog
MohamedHussein27 / UART-With-FIFOs
This repository contains the Verilog implementation of a UART protocol with FIFOs for handling data transmission and reception.
communication-protocol fifo uart uart-protocol uart-verilog verilog-project
Language:Verilog
TahirZia-1 / UART
A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.
fpga-board fpga-programming fpga-soc nexys4ddr rtl simulation systemverilog testbench uart uart-receiver uart-transmitter uart-verilog verilog verilog-hdl verilog-project vivado vivado-hls vivado-simulator
Language:SystemVerilog
TAlmeida003 / uart-core
UART Core com suporte a RTS/CTS para comunicação serial em FPGA. Projeto de Iniciação Científica (CNPq) do Telecore 64, um console portátil em FPGA que integra jogos 2D e controle de robôs, unindo sistemas embarcados, teleoperação e redes.
fpga uart uart-controller uart-interface uart-protocol uart-verilog verilog uart-model-control
Language:Verilog

uart-verilog

pConst / basic_verilog

ZipCPU / wbuart32

ben-marshall / uart

halftop / Interface-Protocol-in-Verilog

TimRudy / uart-verilog

GLADICOS / UART

addisonElliott / LogiFindFPGATest

yasnakateb / UARTCommunication

kishanpatelec / UART-for-bluetooth-module

Shubhayu-Das / VL504-project

AhmedSobhy01 / uart-verilog

KelvinThomasYB17 / Transferring-data-from-SPI-to-UART-using-BMP280-sensor-with-Verilog

KevinWang96 / UART_Verilog_Based

mwbryant / uart-CI

TheLeopardsH / UART

Wissance / QuickRS232

Abd-El-Rahman-Sabry / processing-unit-with-uart

BrunoBMoura / BM_CORE

ColtonBeery / UART_TX

djkabutar / test_mipi_encoder_decoder

Fahad-Habib / UART-Tx

meeeeet / UART-DesignAndVerification

sidhantp1906 / UART

STjurny / BasicUART

2uger / verilog_uart_hw

fscatox / efes_prj

hl271 / uart_with_fifo

PhatLe15 / Computer-Architecture-Design

sushi0706 / uart

0marAmr / UART-Interface

DatNT018 / FPGA-UART-Transceiver

DatNT018 / fpga-verilog-modules

mengstr / vuart

MohamedHussein27 / UART-With-FIFOs

TahirZia-1 / UART

TAlmeida003 / uart-core