uart-verilog

There are 8 repositories under uart-verilog topic.

pConst / basic_verilog
Must-have verilog systemverilog modules
fpga delay debounce encoder xilinx altera verilog fifo tcl spi-master synchronizer pwm uart uart-protocol uart-verilog uart-tx uart-receiver uart-controller spi-interface hls
Language:Verilog 1434
ZipCPU / wbuart32
A simple, basic, formally verified UART controller
fpga uart uart-verilog verilator wishbone wishbone-bus verilog serialport
Language:Verilog 250
ben-marshall / uart
A simple implementation of a UART modem in Verilog.
hardware fpga verilog verilog-hdl uart uart-verilog
Language:Verilog 77
halftop / Interface-Protocol-in-Verilog
Interface Protocol in Verilog
spi uart-protocol uart-verilog verilog-hdl
Language:Verilog 44
TimRudy / uart-verilog
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
digital-logic eda fpga icestorm iverilog open-hardware verilog-components hardware-designs serialport uart-interface uart-verilog
Language:Verilog 12
addisonElliott / LogiFindFPGATest
This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.
altera quartus-prime logifind fpga verilog verilog-hdl uart-verilog nec-verilog ir-receiver cyclone-iv 7-segment buzzer ep4ce6e22c8n pl2303 easyfpga
Language:Verilog 6
GLADICOS / UART
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
systemc systemc-model uart-verilog gtkwave icarus-verilog uart dut
Language:Verilog 6
kishanpatelec / UART-for-bluetooth-module
uart uart-verilog uart-controller uart-com uart-protocol uart-tx uart-receiver bluetooth hc-05
Language:Verilog 4
TheLeopardsH / UART
Universal Asynchronous Receiver Transmitter
uart uart-verilog uart-receiver verilog fpga receiver-transmitter
Language:Verilog 3
meeeeet / UART-DesignAndVerification
rtl-design-and-verification serial-communication systemverilog uart uart-verilog
Language:SystemVerilog 2
Shubhayu-Das / VL504-project
Displaying images taken from an OV7670/laptop camera
vga basys3 ov7670 uart-verilog
Language:Python 2
2uger / verilog_uart_hw
Verilog UART implementation with Vivado build scripts to test on Zedboard
cocotb uart verilog fpga hardware uart-verilog xilinx-fpga
Language:Verilog 1
BrunoBMoura / BM_CORE
Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.
mips architecture risc-processor uart uart-verilog operating-system
Language:Verilog 1
ColtonBeery / UART_TX
Basys 3 UART Tx for COMPE470L class
uart-tx verilog uart-verilog basys3-fpga
Language:Verilog 1
djkabutar / test_mipi_encoder_decoder
MIPI to multiple peripheral (UART, I2C, SPI, 1-Wire)
mipi uart-verilog verilog
Language:Verilog 1
hl271 / uart_with_fifo
Verilog implementation of UART protocol with integrated FIFO buffer
fifo uart uart-verilog verilog
Language:Verilog 1
KevinWang96 / UART_Verilog_Based
Verilog Modeling of UART Tx and Rx
uart-protocol uart-verilog verilog-hdl
Language:Verilog 1
mwbryant / uart-CI
Basic continous integration testing for verilog projects
verilator verilog fpga uart-verilog uart uart-tx
Language:C++ 1
STjurny / BasicUART
Small light-weight implementation of UART in Verilog.
verilog uart uart-verilog fpga ice40 tinyfpga alchitry serialport
Language:Verilog 1
yasnakateb / UARTCommunication
☎️ UART Communication Implementation in Verilog HDL
verilog iverilog icarus-verilog uart uart-verilog uart-interface uart-protocol serial-communication
Language:Verilog 1
Fahad-Habib / UART-Tx
UART Tx implemented in SystemVerilog from scratch.
digital-system-design uart uart-verilog
Language:SystemVerilog 0
PhatLe15 / Computer-Architecture-Design
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.
mips-processor soc fpga-validation performance-analysis truth-tables uart-verilog
Language:HTML 0
RISCY-Lib / LayersOnLayers
A example of UVM Sequence Layering using UART
systemverilog uart-verilog uvm uvm-verification
0
0marAmr / UART-Interface
Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL
communication-interface digital-design uart-interface uart-rx uart-tx uart-verilog
Language:Verilog
mengstr / vuart
WIP - Smallish UART written in Verilog
verilog uart uart-verilog wip-do-not-use
Language:Verilog
sidhantp1906 / UART
UART implementation using Verilog HDL
rtl uart-protocol uart-verilog verilog xilinx-fpga xilinx-ise
Language:Verilog

uart-verilog

pConst / basic_verilog

ZipCPU / wbuart32

ben-marshall / uart

halftop / Interface-Protocol-in-Verilog

TimRudy / uart-verilog

addisonElliott / LogiFindFPGATest

GLADICOS / UART

kishanpatelec / UART-for-bluetooth-module

TheLeopardsH / UART

meeeeet / UART-DesignAndVerification

Shubhayu-Das / VL504-project

2uger / verilog_uart_hw

BrunoBMoura / BM_CORE

ColtonBeery / UART_TX

djkabutar / test_mipi_encoder_decoder

hl271 / uart_with_fifo

KevinWang96 / UART_Verilog_Based

mwbryant / uart-CI

STjurny / BasicUART

yasnakateb / UARTCommunication

Fahad-Habib / UART-Tx

PhatLe15 / Computer-Architecture-Design

RISCY-Lib / LayersOnLayers

0marAmr / UART-Interface

mengstr / vuart

sidhantp1906 / UART