uart-verilog

There are 8 repositories under uart-verilog topic.

• pConst / basic_verilog

  Must-have verilog systemverilog modules

  fpgadelaydebounceencoderxilinxalteraverilogfifotclspi-mastersynchronizerpwmuartuart-protocoluart-veriloguart-txuart-receiveruart-controllerspi-interfacehls
  Language:Verilog 1657

• ZipCPU / wbuart32

  A simple, basic, formally verified UART controller

  fpgaserialportuartuart-verilogverilatorverilogwishbonewishbone-bus
  Language:Verilog 282

• ben-marshall / uart

  A simple implementation of a UART modem in Verilog.

  fpgahardwareuartuart-verilogverilogverilog-hdl
  Language:Verilog 101

• halftop / Interface-Protocol-in-Verilog

  Interface Protocol in Verilog

  spiuart-protocoluart-verilogverilog-hdl
  Language:Verilog 47

• TimRudy / uart-verilog

  A simple 8 bit UART implementation in Verilog, with tests and timing diagrams

  digital-logicedafpgahardware-designsicestormiverilogopen-hardwareserialportuart-interfaceuart-verilogverilog-components
  Language:Verilog 19

• GLADICOS / UART

  This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog

  systemcsystemc-modeluart-veriloggtkwaveicarus-veriloguartdut
  Language:Verilog 7

• addisonElliott / LogiFindFPGATest

  This is a Quartus Prime FPGA project testing the functionality of the LogiFind Altera Cyclone IV EP4CE6E22C8N Development Board. This product can also be found on eBay where I bought it from. I hope to provide base code that will help others in their learning with this development board.

  alteraquartus-primelogifindfpgaverilogverilog-hdluart-verilognec-verilogir-receivercyclone-iv7-segmentbuzzerep4ce6e22c8npl2303easyfpga
  Language:Verilog 6

• kishanpatelec / UART-for-bluetooth-module

  uartuart-veriloguart-controlleruart-comuart-protocoluart-txuart-receiverbluetoothhc-05
  Language:Verilog 4

• Shubhayu-Das / VL504-project

  Displaying images taken from an OV7670/laptop camera

  vgabasys3ov7670uart-verilog
  Language:Python 2

• TheLeopardsH / UART

  Universal Asynchronous Receiver Transmitter

  uartuart-veriloguart-receiververilogfpgareceiver-transmitter
  Language:Verilog 2

• yasnakateb / UARTCommunication

  ☎️ UART Communication Implementation in Verilog HDL

  verilogiverilogicarus-veriloguartuart-veriloguart-interfaceuart-protocolserial-communication
  Language:Verilog 2

• 2uger / verilog_uart_hw

  Verilog UART implementation with Vivado build scripts to test loopback on Xilinx Arty board

  cocotbuartverilogfpgahardwareuart-verilogxilinx-fpga
  Language:Python 1

• BrunoBMoura / BM_CORE

  Single-cycle MIPS-based processor architecture, designed as the final project for the Laboratory of Computer Architecture and Organization course and later enhanced for both Laboratory of Operational Systems and Laboratory of Computer Networks courses.

  architecturemipsoperating-systemrisc-processoruartuart-verilog
  Language:Verilog 1

• ColtonBeery / UART_TX

  Basys 3 UART Tx for COMPE470L class

  basys3-fpgauart-txuart-verilogverilog
  Language:Verilog 1

• djkabutar / test_mipi_encoder_decoder

  MIPI to multiple peripheral (UART, I2C, SPI, 1-Wire)

  mipiuart-verilogverilog
  Language:Verilog 1

• Fahad-Habib / UART-Tx

  UART Tx implemented in SystemVerilog from scratch.

  digital-system-designuartuart-verilog
  Language:SystemVerilog 1

• hl271 / uart_with_fifo

  Verilog implementation of UART protocol with integrated FIFO buffer

  fifouartuart-verilogverilog
  Language:Verilog 1

• KevinWang96 / UART_Verilog_Based

  Verilog Modeling of UART Tx and Rx

  uart-protocoluart-verilogverilog-hdl
  Language:Verilog 1

• meeeeet / UART-DesignAndVerification

  rtl-design-and-verificationserial-communicationsystemveriloguartuart-verilog
  Language:SystemVerilog 1

• mwbryant / uart-CI

  Basic continous integration testing for verilog projects

  fpgauartuart-txuart-verilogverilatorverilog
  Language:C++ 1

• STjurny / BasicUART

  Small light-weight implementation of UART in Verilog.

  veriloguartuart-verilogfpgaice40tinyfpgaalchitryserialport
  Language:Verilog 1

• KelvinThomasYB17 / Transferring-data-from-SPI-to-UART-using-BMP280-sensor-with-Verilog

  Transferring data from SPI to UART using BMP280 sensor with Verilog

  bmp280de10-litefpgamodelsimspispi-protocolspi-veriloguart-protocoluart-verilogverilog
  Language:Verilog 0

• PhatLe15 / Computer-Architecture-Design

  Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.

  fpga-validationmips-processorperformance-analysissoctruth-tablesuart-verilog
  Language:HTML 0

• sushi0706 / uart

  verilog-uart

  modelsimuart-protocoluart-rxuart-txuart-verilogverilog
  Language:Verilog 0

• 0marAmr / UART-Interface

  Design of Universal Asynchronous Receiver Transmitter Interface using verilog HDL

  communication-interfacedigital-designuart-interfaceuart-rxuart-txuart-verilog
  Language:Verilog

• mengstr / vuart

  WIP - Smallish UART written in Verilog

  uartuart-verilogverilogwip-do-not-use
  Language:Verilog

• sidhantp1906 / UART

  UART implementation using Verilog HDL

  rtluart-protocoluart-verilogverilogxilinx-fpgaxilinx-ise
  Language:Verilog