wishbone

There are 1 repository under wishbone topic.

ZipCPU / zipcpu
A small, light weight, RISC CPU soft core
cpu cross-compiler fpga risc-cpu soft-core verilator verilog wishbone wishbone-bus zipcpu
Language:Verilog 1305
ZipCPU / wb2axip
Bus bridges and other odds and ends
axi-bus fpga gplv3 wishbone wishbone-bus xilinx xilinx-vivado
Language:Verilog 491
ZipCPU / wbuart32
A simple, basic, formally verified UART controller
fpga uart uart-verilog verilator wishbone wishbone-bus verilog serialport
Language:Verilog 282
ZipCPU / sdspi
SD-Card controller, using either SPI, SDIO, or eMMC interfaces
axi emmc fpga sd-card sd-interface sdio spi-interface verilator verilog verilog-components wishbone wishbone-bus
Language:Verilog 210
ZipCPU / autofpga
A utility for Composing FPGA designs from Peripherals
c-plus-plus fpga verilator verilog wishbone wishbone-bus
Language:C++ 168
ZipCPU / openarty
An Open Source configuration of the Arty platform
arty fpga fpga-soc verilator wishbone wishbone-bus zipcpu
Language:Verilog 122
jakubcabal / uart-for-fpga
Simple UART controller for FPGA written in VHDL
controller cyc1000 fpga ghdl simulation uart uart-controller uart-loopback vhdl wishbone wishbone-bus
Language:VHDL 91
ZipCPU / wbscope
A wishbone controlled scope for FPGA's
fpga verilog verilator debugging-tools wishbone-bus wishbone
Language:Verilog 73
lxp32-cpu
lxp32 / lxp32-cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
fpga cpu risc soft-core wishbone wishbone-bus risc-cpu risc-processor vhdl assembler assembly
Language:Assembly 59
ZipCPU / dbgbus
A collection of debugging busses developed and presented at zipcpu.com
debugging-tools fgpa verilator verilog wishbone wishbone-bus
Language:Verilog 36
ZipCPU / s6soc
CMod-S6 SoC
zipcpu fpga fpga-soc verilator wishbone wishbone-bus
Language:Verilog 36
stnolting / wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
vhdl fpga neorv32 wishbone spi xip flash memory
Language:VHDL 21
ZipCPU / wbfmtx
A wishbone controlled FM transmitter hack
fm-transmitter fpga hack verilog verilog-components wishbone wishbone-bus
Language:Verilog 21
BLangOS / VexRiscV_with_HW-GDB_Server
VexRiscV system with GDB-Server in Hardware
microcontroller vhdl fpga-soc vexriscv gdbserver rsp wishbone c-language risc-v
Language:VHDL 20
lingbai-kong / computer-system
同济大学CS《计算机系统实验》实验二TongJi University CS computer system experiment assignment 2《自己动手写 CPU》SOPC实现与操作系统移植
fpga big-endian cpu dynamic-pipelines uart wishbone gpio sdcard ddr2 tongji-university ucosii sopc openmips
Language:Verilog 17
WbXbc
hotwolf / WbXbc
HDL components to build a customized Wishbone crossbar switch
crossbar hdl verilog wishbone
Language:SystemVerilog 14
pbing / ibex_wb
RISC-V Ibex core with Wishbone B4 interface
risc-v riscv systemverilog wishbone wishbone-bus
Language:HTML 14
merledu / caravan
A caravan equipped with API for creating bus protocols in Chisel with ease.
amba bus-protocols caravan chisel-generator chisel3 on-chip-network wishbone
Language:Scala 13
MPSoC-DMA
PacoReinaCampo / MPSoC-DMA
Direct Access Memory for MPSoC
ahb3-lite wishbone
Language:SystemVerilog 12
fpga-3-softcores
rschlaikjer / fpga-3-softcores
Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware
fpga risc-v softcore wishbone
Language:Verilog 10
semahawk / wishbone
Trying to learn Wishbone by implementing few master/slave devices
wishbone wishbone-bus verilog verilog-hdl
Language:SystemVerilog 9
bnossum / midgetv
rv32i/rv32im/rv32imc for iCE40. Wishbone interface.
ice40 ice40up5k iceblink40-hx1k icebreaker lattice microcode riscv rv32i upduino2 verilator verilog wishbone yosys
Language:Verilog 8
ZipCPU / wbicapetwo
Wishbone to ICAPE interface conversion
wishbone fpga verilator iprog-command xilinx gplv3
Language:Verilog 8
daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
clock-generator hdl rtl spi spi-interface spi-master spi-protocol spi-slave testbench verilog verilog-code verilog-hdl verilog-project verilog-rtl-model wishbone wishbone-master
Language:Verilog 7
jracevedob / Processor-Design
In this repository, it is presented the whole design of a functional RISC processor. Therefore, the design of every functional block (arithmetic and control units among others) is written in Verilog and the verification of every single block is provided.
verilog processordesign wishbone zmc highperformance
Language:Verilog 4
panda5mt / qf_wbfpga_pio
QuickLogic EOS S3:Cortex-M4 to FPGA Fabric via WISHBONE bus Sample Code with 8bit CAMERA-IF
efpga quicklogic wishbone
Language:C 4
semahawk / icarium
Trying to implement a soft core SoC
verilog verilog-hdl system-on-chip wishbone wishbone-bus softcore soft-core
Language:Verilog 4
MPSoC-GPIO
PacoReinaCampo / MPSoC-GPIO
General Purpose Input Output for MPSoC
ahb3-lite wishbone
Language:SystemVerilog 3
MPSoC-MPI
PacoReinaCampo / MPSoC-MPI
Message Passing Interface for MPSoC
ahb3-lite wishbone
Language:SystemVerilog 3
MPSoC-MPRAM
PacoReinaCampo / MPSoC-MPRAM
Multi-Port RAM for Instruction & Data for MPSoC
ahb3-lite wishbone
Language:SystemVerilog 3
MPSoC-SPRAM
PacoReinaCampo / MPSoC-SPRAM
Single-Port RAM for Instruction & Data for MPSoC
ahb3-lite wishbone
Language:SystemVerilog 3
MPSoC-UART
PacoReinaCampo / MPSoC-UART
Universal Asynchronous Receiver-Transmitter for MPSoC
ahb3-lite wishbone
Language:SystemVerilog 3
pbing / J1_WB
Forth CPU J1 in SystemVerilog and Wishbone interface
systemverilog wishbone-bus wishbone forth-cpu
Language:SystemVerilog 3
batuhanates / ibex_wb
RISC-V Ibex core with Wishbone B4 interface
riscv ibex wishbone fpga
Language:C 2
cyber-murmel / nmigen-wishbone-examples
A collection of nMigen examples based on the OpenCores WISHBONE Tutorial https://cdn.opencores.org/downloads/wbspec_b4.pdf#page=91
nmigen nmigen-soc wishbone wishbone-bus fpga fpga-soc
Language:Python 2
MPSoC-MSI
PacoReinaCampo / MPSoC-MSI
Master Slave Interface for MPSoC
ahb3-lite wishbone
Language:SystemVerilog 2

wishbone

ZipCPU / zipcpu

ZipCPU / wb2axip

ZipCPU / wbuart32

ZipCPU / sdspi

ZipCPU / autofpga

ZipCPU / openarty

jakubcabal / uart-for-fpga

ZipCPU / wbscope

lxp32 / lxp32-cpu

ZipCPU / dbgbus

ZipCPU / s6soc

stnolting / wb_spi_bridge

ZipCPU / wbfmtx

BLangOS / VexRiscV_with_HW-GDB_Server

lingbai-kong / computer-system

hotwolf / WbXbc

pbing / ibex_wb

merledu / caravan

PacoReinaCampo / MPSoC-DMA

rschlaikjer / fpga-3-softcores

semahawk / wishbone

bnossum / midgetv

ZipCPU / wbicapetwo

daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules

jracevedob / Processor-Design

panda5mt / qf_wbfpga_pio

semahawk / icarium

PacoReinaCampo / MPSoC-GPIO

PacoReinaCampo / MPSoC-MPI

PacoReinaCampo / MPSoC-MPRAM

PacoReinaCampo / MPSoC-SPRAM

PacoReinaCampo / MPSoC-UART

pbing / J1_WB

batuhanates / ibex_wb

cyber-murmel / nmigen-wishbone-examples

PacoReinaCampo / MPSoC-MSI