fredrequin

j68_cpu

Small microcoded 68000 verilog softcore

verilator_xilinx

Re-coded Xilinx primitives for Verilator use

fpga_1943

Verilog re-implementation of the famous CAPCOM arcade game

JiVe

Small micro-coded RISC-V softcore

verilator_gowin

Re-coded Gowin GW1N primitives for Verilator use

fx68k

FX68K 68000 cycle accurate SystemVerilog core

at_apollo_device

AT-Apollo.device v5.03 source code from 1999 Aminet release

verilator_helpers

C++ objects to help verilator simulations

exactstep

Instruction set simulator for RISC-V, MIPS and ARM-v6m

nmos_sim

Simulate old NMOS logic using Kicad and Verilator

nvc

VHDL compiler and simulator

c--

c++ Bjarne Stroustrup

core_sdram_axi4

SDRAM controller with AXI4 interface

docker_open-src-cvc

Dockerfile for OSS CVC verilog simulator

hdlConvertor

Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTL4

HiVee

Multi threaded light weight RISC-V softcore

maixduino-genplus

Genesis-Plus-GX based MEGADRIVE/GENESIS emulator for the Maixduino

open-src-cvc

Mirror of tachyon-da cvc Verilog simulator

riscv

RISC-V CPU Core (RV32IM)

riscv-compliance

verilator

Verilator open-source SystemVerilog simulator and lint system

xvcd-anita

XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.

yosys

Yosys Open SYnthesis Suite

zephyr

Primary GIT Repository for the Zephyr Project