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Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
An FPGA implementation of Cummings' Asynchronous FIFO
A hardware implementation of component labeling
Parameterized synchronous FIFO buffer implementation in Verilog with pointer-based read/write operations, full/empty flags, and comprehensive testbenches. Features synthesizable design with waveform analysis and gate-level schematic verification.