synthesizable

There are 0 repository under synthesizable topic.

sgherbst / svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
verilog systemverilog fixed-point floating-point synthesizable synthesis simulation vivado xcelium icarus-verilog iverilog xrun irun ncsim vcs icarus verilator
Language:SystemVerilog 41
sgherbst / msdsl
Automatic generation of real number models from analog circuits
analog mixed-signal ams model generator analog-circuits python synthesizable synthesis simulation rnm real-number-modeling
Language:Python 34
SnrNotHere16 / Asynchronous-FIFO
An FPGA implementation of Cummings' Asynchronous FIFO
fpga fpga-programming xilinx-fpga xilinx-vivado nexys4ddr verilog rtl fifo asynchronous-fifo register-transistor-level xilinx hardware-description-language synthesis synthesizable digilent digilent-nexys-4-board systemverilog uvm uvm-verification universal-verification-methodology
Language:SystemVerilog 3
erictaur / Component-Labeler
A hardware implementation of component labeling
component-labeler verilog synthesizable
Language:Verilog 1