synthesizable

There are 0 repository under synthesizable topic.

sgherbst / svreal
Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats
verilog systemverilog fixed-point floating-point synthesizable synthesis simulation vivado xcelium icarus-verilog iverilog xrun irun ncsim vcs icarus verilator
Language:SystemVerilog 48
sgherbst / msdsl
Automatic generation of real number models from analog circuits
ams analog analog-circuits generator mixed-signal model python real-number-modeling rnm simulation synthesis synthesizable
Language:Python 44
SnrNotHere16 / Asynchronous-FIFO
An FPGA implementation of Cummings' Asynchronous FIFO
fpga fpga-programming xilinx-fpga xilinx-vivado nexys4ddr verilog rtl fifo asynchronous-fifo register-transistor-level xilinx hardware-description-language synthesis synthesizable digilent digilent-nexys-4-board systemverilog uvm uvm-verification universal-verification-methodology
Language:SystemVerilog 5
erictaur / Component-Labeler
A hardware implementation of component labeling
component-labeler verilog synthesizable
Language:Verilog 1
VLSI-Shubh / FIFO
Parameterized synchronous FIFO buffer implementation in Verilog with pointer-based read/write operations, full/empty flags, and comprehensive testbenches. Features synthesizable design with waveform analysis and gate-level schematic verification.
digital-design fifo memory-buffer rtl synthesizable verilog
Language:Verilog