ghdl

There are 1 repository under ghdl topic.

ghdl / ghdl
VHDL 2008/93/87 simulator
vhdl ghdl simulator testbench compiler gcc llvm hardware hacktoberfest
Language:VHDL 2231
olofk / edalize
An abstraction library for interfacing EDA tools
eda fpga fossi xilinx altera lattice yosys synthesis simulation verilog vhdl systemverilog verilator icarus-verilog modelsim riviera-pro ghdl icestorm spyglass vivado
Language:Python 594
suoto / hdl_checker
Repurposing existing HDL tools to help writing better code
vhdl modelsim xilinx verilog systemverilog python hdl xilinx-vivado syntax-checker lsp-server vivado-simulator ghdl vim hdl-checker language-server coc-nvim questasim mentor-msim vim-ale emacs-lsp
Language:Python 184
jakubcabal / spi-fpga
SPI master and SPI slave for FPGA written in VHDL
spi-slave spi-master fpga vhdl spi controller spi-loopback spi-controller cyc1000 accelerometer ghdl
Language:VHDL 159
jakubcabal / uart-for-fpga
Simple UART controller for FPGA written in VHDL
uart fpga uart-controller vhdl controller wishbone wishbone-bus uart-loopback simulation ghdl cyc1000
Language:VHDL 89
PyFPGA / pyfpga
A Python package to use FPGA development tools programmatically.
fpga python tcl xilinx intel microchip lattice ghdl ise libero quartus vivado yosys nextpnr icestorm trellis altera microsemi actel amd
Language:Python 77
Paebbels / JSON-for-VHDL
A JSON library implemented in VHDL.
vhdl json parser fileformat fpga xilinx lattice modelsim questasim ghdl simulation synthesis
Language:VHDL 74
tmeissner / psl_with_ghdl
Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
vhdl psl ghdl yosys formal-verification assertions symbiyosys functional-coverage
Language:VHDL 60
stnolting / neorv32-setups
📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
fpga ghdl intel lattice neorv32 risc-v soc verilog vhdl xilinx yosys
Language:VHDL 53
tmeissner / formal_hw_verification
Trying to verify Verilog/VHDL designs with formal methods and tools
vhdl systemverilog yosys formal-verification verilog symbiyosys psl ghdl
Language:VHDL 41
ghdl / docker
Scripts to build and use docker images including GHDL
ghdl dockerfiles simulation testbench vhdl hardware ci gtkwave vunit actions yosys nextpnr icestorm synthesis pnr verilog prjtrellis openocd
Language:Shell 40
tmeissner / cryptocores
cryptography ip-cores in vhdl / verilog
vhdl verilog fpga ghdl testbenches cryptography
Language:VHDL 40
neorv32-verilog
stnolting / neorv32-verilog
♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
asic fpga ghdl neorv32 verilog icarus-verilog
Language:Verilog 39
dbhi / vboard
Virtual development board for HDL design
hdl vhdl verilog ghdl verilator vhpidirect vpi fli cosim
Language:VHDL 37
tmeissner / libvhdl
Library of reusable VHDL components
vhdl testbenches osvvm psl verification fpga coverage ghdl assertions formal-verification
Language:VHDL 25
stnolting / neorv32-riscof
✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
neorv32 risc-v verification riscof sail-riscv processor riscv ghdl vhdl isa
Language:Python 24
SalvatoreBarone / CNN-VHDL
A library of VHDL components for Neural Networks
artificial-intelligence artificial-neural-networks convolutional-neural-networks lenet-5 vhdl ghdl xilinx-fpga virtex approximation approximate-computing approximate-algorithms
Language:C++ 14
tmeissner / gatemate_experiments
Experiments with Cologne Chip's GateMate FPGA architecture
fpga ghdl vhdl yosys gatemate verilog
Language:VHDL 14
dominiksalvet / risc63
Custom 64-bit pipelined RISC processor
64-bit custom processor isa architecture pipeline microarchitecture rtl vhdl ghdl makefile risc cpu open-source hardware alu interrupts testbench thesis bachelor-thesis
Language:VHDL 13
rodrigomelo9 / verifying-foss-hdl-synthesizers
a project to check the FOSS synthesizers against vendors EDA tools
yosys ghdl ghdl-yosys-plugin foss-synthesizers pyfpga ise vivado quartus iverilog verilator
Language:Makefile 12
JulyWitch / vhdl_ghdl_examples
Simple VHDL examples using ghdl as compiler and wave generating
ghdl vhdl gtkwa scansion vhdl-examples vhdl-code vhdl-testbench
Language:VHDL 11
machitgarha / parvaj
Easy and fast VHDL simulation tool, integrating GHDL and GTKWave
automated build console-application ghdl gtkwave simulation test vhdl
Language:PHP 11
umarcor / SIEAV
Co-simulation and behavioural verification with VHDL, C/C++ and Python/m
co-simulation cosim ghdl vunit octave matlab gtkwave
Language:VHDL 10
dominiksalvet / vhdl-collection
Collection of generic VHDL modules
vhdl circuit hardware rom ram fifo lifo pwm seven-segment clock reusable components memory parallel serial collection generic ghdl xilinx fpga
Language:VHDL 8
marph91 / icestick-remote
Remote control in VHDL, which fits on a Lattice icestick.
icestick vhdl ghdl fpga hardware ice40
Language:VHDL 8
dbhi / containers
Containerized open and free development tools for Dynamic Binary Hardware Injection (DBHI)
docker podman ghdl vunit dynamorio gtkwave octave arm pynq zynq multiarch
Language:Dockerfile 7
nobodywasishere / upduino-projects
Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
upduino upduino2 vhdl ghdl toolchain ghdl-yosys-plugin icestorm
Language:VHDL 6
chuckb / ghdl-interactive-sim
Interactive GHDL simulation of a VHDL adder using Python, Cocotb, and pygame
python ghdl cocotb vpi pygame simulator vhdl gui
Language:Python 5
miree / gvi
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
cosimulation verilog vhdl opensource ghdl verilator
Language:C++ 5
PLC2 / Solution-StopWatch
Professional VHDL Class Solution - StopWatch
plc2 training class vhdl stopwatch vivado xilinx ghdl synthesis rtl simulation
Language:VHDL 5
vhdl-docker-template
YoussefRaafatNasry / vhdl-docker-template
Template for creating VHDL project using docker
ghdl gtkwave vuint docker vscode
Language:VHDL 5
vscode-ghdl-interface
johannesbonk / vscode-ghdl-interface
A tool to invoke ghdl/gtkwave functions, including error highlighting
vscode vscode-extension vscode-plugin ghdl-interface ghdl gtkwave
Language:JavaScript 4
Kazhuu / vhdl-examples
VHDL examples for a different kind of topics
vhdl modelsim vim-hdl vim hdlcc examples example example-code example-codes example-project ghdl
Language:VHDL 4
AsadpourMohammad / VHDL-Projects
VHDL Mini Projects
cads computer-aided-design ghdl vhdl
Language:VHDL 3
PyFPGA / openflow
A Python library, and CLI utilities, which solves HDL-to-bitstream based on FOSS.
ghdl yosys nextpnr icestorm prjtrellis fpga
Language:Python 3
SethGower / dotfiles
The configuration files for my linux setup on my laptop and desktop.
linux configuration-files dotfiles i3-gaps polybar neovim vim tmux ghdl yadm
Language:Shell 3

ghdl

ghdl / ghdl

olofk / edalize

suoto / hdl_checker

jakubcabal / spi-fpga

jakubcabal / uart-for-fpga

PyFPGA / pyfpga

Paebbels / JSON-for-VHDL

tmeissner / psl_with_ghdl

stnolting / neorv32-setups

tmeissner / formal_hw_verification

ghdl / docker

tmeissner / cryptocores

stnolting / neorv32-verilog

dbhi / vboard

tmeissner / libvhdl

stnolting / neorv32-riscof

SalvatoreBarone / CNN-VHDL

tmeissner / gatemate_experiments

dominiksalvet / risc63

rodrigomelo9 / verifying-foss-hdl-synthesizers

JulyWitch / vhdl_ghdl_examples

machitgarha / parvaj

umarcor / SIEAV

dominiksalvet / vhdl-collection

marph91 / icestick-remote

dbhi / containers

nobodywasishere / upduino-projects

chuckb / ghdl-interactive-sim

miree / gvi

PLC2 / Solution-StopWatch

YoussefRaafatNasry / vhdl-docker-template

johannesbonk / vscode-ghdl-interface

Kazhuu / vhdl-examples

AsadpourMohammad / VHDL-Projects

PyFPGA / openflow

SethGower / dotfiles