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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
A Dockerfile with a collections of ready to use open source EDA tools: Yosys, SimbiYosys (with Z3, boolector and Yices2), nextpnr-ice40, netxpnr-ecp5, nextpnr-gowin, Amaranth HDL, Silice and Verilator.
Trying to verify Verilog/VHDL designs with formal methods and tools
Solving Sudokus using open source formal verification tools
Bazel rules for Symbiyosys.
SymbiYosys (sby) Formal Verification
Prettyosys is an easy-to-use and visually appealing wrapper for Symbioysys