pll

There are 1 repository under pll topic.

lakshmi-sathi / avsdpll_1v8
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
analog-circuit asic charge-pump clock-multiplier ic intellectual-property manufacturable phase-detector pll rtl2gds
108
ZipCPU / dpll
A collection of phase locked loop (PLL) related projects
fpga gplv3 pll verilator verilog
Language:Verilog 99
pavelmc / Si5351mcu
Arduino Si5351 library tuned for size and click free.
arduino si5351 bitx20 click-free pll dds vfo hamradio homebrew co7wt
Language:C++ 63
muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system
This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, with a comparison between using an LC VCO and using a Ring VCO.
analog-design cadence-virtuoso matlab pll veriloga
Language:MATLAB 57
iDoka / eda-scripts
Collect of various scripts for helping work with EDA-tools (ASIC, FPGA, etc)
asic design-automation eda fpga gitattributes gitignore mmcm pll ucf versioning vivado xdc xilinx
Language:Shell 29
super1207 / FOC
sensorless fixed point foc use smo and pll in stm32
bldc foc motor pll pmsm sensorless smc smo six-wave
Language:C 21
muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
analog analog-circuit analog-design cadence-virtuoso pll transceiver
20
r4d10n / iCEstick-hacks
iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
fm transmitter icestick ice40 pll
Language:Verilog 18
parasgidd / avsdpll_3v3
This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship.
pll chip-clock-multiplier frequency-divider processor-chip hactoberfest
Language:SourcePawn 15
NightIsDark / RFFC
RFFC2071 C8051F330
rffc2071 pll
Language:C 13
ilyajob05 / verilog_modules
verilog modules
verilog rmii i2c spi uart usart timer memory 7-segment synchronization pll nexys4 nexys-4-spartan-3e nexys4-board fpga xilinx xilinx-fpga
Language:Verilog 12
qff233 / FOC
FOC driver library written in Rust
foc pid pll rust bldc electronic-speed-controller embedded field-oriented-control firmware motor-controller pmsm
Language:Rust 12
sascha-kirch / Bit_Error_Tester
This project implements a bit error rate tester. A PRBS (pseudo random bit sequence) is generated that can feed the DUT. The receiver compares the internally delayed transmitted signals with received signal and counts up an error counter if their logic levels differ.
fpga prbs-generator bit-error-rate pll clock-generator verilog
Language:Verilog 12
XiangYyang / SOGI-PLL
Single-Phase PLL / Second-Order Generalized Integrators Phase Lock Loop
control-systems discrete-systems pll power-electronics sogi-pll
Language:C++ 10
abranhe / react-pll
<Pll/> React Programming Language Logo Component.
pll programming-languages-logos react
Language:JavaScript 9
aieask / vsd_pll
8x PLL Clock Multiplier PLL Design with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving an 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
asic ic pll design analog-design google-skywater-pdk ngspice magic rtl2gds gds charge-pum clock-multiplier voltage-controlled-oscillator open-source open-source-hardware open-source-project
9
infini8-13 / riscv-ms-soc
A RISC-V Mixed Signal System-on-Chip(SoC) produced by integrating RVMyth RISC-V Core with Phase Locked Loop(PLL) as a clock multiplier
fpga mixed-signal pll risc-v system-on-chip tl-verilog verilog
Language:Verilog 9
zhinst / blogs
Support files for blog posts of Zurich Instruments
awg boxcar lockin pid pll quantum-computing
Language:Jupyter Notebook 9
Enanter / ADPLL
All Digital Phase-Locked Loop
pll systemverilog
Language:Tcl 8
americodias / sca_pll
PLL Simulator in SystemC-AMS
pll systemc systemc-ams
Language:C++ 7
microchip-pic-avr-solutions / mchv3-dspic33ck256mp508-an1206
Sensorless FOC (PLL estimator) of AC induction motor with field weakening
motor-control acim foc pll
Language:C 7
Yongxiang-Guo / ADF4351_PLL
Using ADF4351/PLL to get the frequency you want by STM32F103 !
adf4351 pll stm32f103
Language:C 6
sv1onw / Si5351_OLED_DFS
Very minimalistic 20meter transceiver Digital Frequency Synthesizer with 0.96 or 1.3 inch 128x64 OLED Display for Ham-radio use
si5351a pll digital frequency synthesizer oled display ssb transceiver ham-radio
Language:C++ 5
Eyantra698Sumanto / VSDOpen_PLL_Tutorial
This repo contains documentation of the "VSD Open On-Chip Clock Multiplier (PLL) on OSU180" tutorial.
vsd pll on-chip clock osu180 layout magic vco frequency-divider vlsi intergrated circuit fabrication
4
frifle / adventskalender
Ein alternativer Elektronik-Adventskalender für das Jahr 2023
4046 adventskalender basteln elektronik pll puzzle
Language:HTML 4
ranjith-dhananjaya / 20GHz-integer-N-PLL-in-65nm-CMOS-process
Design of a frequency synthesizer to generate the 20 GHz output signal from 100 MHz input using 𝑉𝐷𝐷 of 1.2V in Cadence 65nm CMOS process
analog capacitor charge-pump design frquency-divider ic-design-project inductor locking pfd pll vco
4
sh123 / MC145192-arduino
MC145192 PLL synthesizer control library for Arduino
amateur-radio amateurradio arduino arduino-library pll synthesizer transceiver uhf vhf
Language:C++ 4
sv1onw / Si5351_OLED_DFS_CW
Modified version of Si5351_OLED_DFS for simple CW TX use or DC receiver.
si5351a pll digital frequency synthesizer oled display cw transmitter ham-radio
Language:C++ 4
merledu / jigsaw
A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
chisel-generator chisel3 gpio peripherals pll soc spi-flash spi-protocol sram uart-protocol
Language:Scala 3
oliviercotte / All-digital-modulator
All digital lowpas delta-sigma modulator (+digital up-converter) tune to fmax = 9 MHz
digital digital-modulator digital-signal-processing dsp fir-filter fpga iir-filter interpolation jtag matlab overclock oversampling pll sigma-delta-modulation signal-processing simulink spartan6 up-conversion vhdl zynq-7045
Language:HTML 3
PU2REO / Si5351ArduinoLite
Library for the Si5351A (10 MSOP - 3 Clocks Only) clock generator IC in the Arduino environment , based on NT7S library.
arduino-library clock-generator ham-radio pll si5351a
Language:C++ 3
tejokrishna10 / pll-design-osu-180nm
This repository presents design of on-chip clock multiplier(8X PLL) using open source EDA tool OSU 180nm technology node
180nm chip-clock-multiplier pll project
3
FPGAwars / icePLL
PLL collection for IceStudio
icestudio pll fpga fpgawars
Language:JavaScript 2
lmartorella / lm7001_si470_bridge
LM7001 to Si4703 FM tuner bridge
si4703 fm-radio pll microchip-pic repair pioneer xc8
Language:Makefile 2
saiakarsh193 / PyCube-Solver
Rubik's cube solver using CFOP
rubiks-cube rubiks-cube-solver rubiks-cube-simulator rubiks-cube-scrambler cfop parser python f2l oll pll
Language:Python 2
smonteillet / pll-trainer
Train your PLL skills on Rubik's cube with this groovy script
groovy rubiks-cube rubiks-cube-scrambler rubiks pll groovy-script cfop scramble
Language:Groovy 2

pll

lakshmi-sathi / avsdpll_1v8

ZipCPU / dpll

pavelmc / Si5351mcu

muhammadaldacher / Analog-Design-of-1.9-GHz-PLL-system

iDoka / eda-scripts

super1207 / FOC

muhammadaldacher / Analog-design-of-10-GbaseKR-high-speed-serial-link-transceiver-in-65-nm-CMOS

r4d10n / iCEstick-hacks

parasgidd / avsdpll_3v3

NightIsDark / RFFC

ilyajob05 / verilog_modules

qff233 / FOC

sascha-kirch / Bit_Error_Tester

XiangYyang / SOGI-PLL

abranhe / react-pll

aieask / vsd_pll

infini8-13 / riscv-ms-soc

zhinst / blogs

Enanter / ADPLL

americodias / sca_pll

microchip-pic-avr-solutions / mchv3-dspic33ck256mp508-an1206

Yongxiang-Guo / ADF4351_PLL

sv1onw / Si5351_OLED_DFS

Eyantra698Sumanto / VSDOpen_PLL_Tutorial

frifle / adventskalender

ranjith-dhananjaya / 20GHz-integer-N-PLL-in-65nm-CMOS-process

sh123 / MC145192-arduino

sv1onw / Si5351_OLED_DFS_CW

merledu / jigsaw

oliviercotte / All-digital-modulator

PU2REO / Si5351ArduinoLite

tejokrishna10 / pll-design-osu-180nm

FPGAwars / icePLL

lmartorella / lm7001_si470_bridge

saiakarsh193 / PyCube-Solver

smonteillet / pll-trainer